Investigation On Improving Clearing Polishing Planarization Performance Of GLSI Multilayer Copper Interconnection

With the continuous improvement of integrated circuit integration and technology node size decreases,multilayer interconnection chemical mechanical planarization has become the only effective way to achieve global planarization of wafer in the field of microelectronics.In view of acid polishing slurry commonly used at home and abroad owning disadvantages of containing inhibitor?BTA?,quality of wafer after CMP being hard to meet requirements of microelectronics technology and being difficult to clean,the paper adopted a new type of alkaline polishing slurry self-developed which is composed of simple elements.It doesn't contain toxic BTA and erode polishing equipment.Aiming at the worldwide problem,for example,dishing extends seriously,uniformity is difficult to meet the requirements of 65nm node and demands of global planarization improve unceasingly,we firstly combined theoretical models such as remained layer,priority physical adsorption,self-passivation as well as mass transmission and characteristics of chelating agent and surfactant researched independently.By researching polishing theory,routes,methods and material,planarization performance of multilayer copper interconnection has been improved effectively.The paper analyzed core function of clearing polishing,main factors causing key question and optimal technical solution to solve the problem.On the basis of determining basic rule of clearing polishing,material composition and optimization process technology has been confirmed and groud-breaking planarization effect has been obtained finally.Effect of nonionic surfactant on surface uniformity and topography of wafer post clearing polishing was researched.Based on the theory of mass transfer and priority adsorption,using FA/O composite surfactant increased the thickness of remained layer in concave and mass transfer time which effectively controlled the removal rate of concave copper.The experiment ensured that when the concentration of surfactant was 60ml/L removal rate of clearing polishing was 2268?/min which meets the industrial requirement about removal rate of clearing polishing about 2000?/min.Surface uniformity of wafer decreased from5%which can be commonly reached abroad to 3%below.Surface roughness of wafer reached 0.62nm and dishing post clearing polishing ranged from 800?which is the required value of industrial demand for 65nm node to 723?.Thus extension of dishing was effectively controlled and high level local and global planarization was achieved.As for the polishing process,effect of polishing process on clearing polishing performance was analyzed and a set of optimized process parameters was obtained:polishing pressure was1.0 psi,polishing slurry flow was 300ml/min,polishing head rotation speed was 87rpm,rotation speed of polishing pad was 93rpm.Using IC1000 polishing pad,under the premise of ensuring clearing polishing entirely remove the residual copper and removal rate of barrier layer was zero,dishing was controlled effectively.Otherwise,the paper studied electrochemical properties of Cu electrode in clearing polishing electrolyte of different H₂O₂ concentration.When H₂O₂ content was 35ml/L,E_corr of copper electrode and passivation of concave copper film reached maximum.Extension of dishing was optimized and controlled effectively.Polishing terminal point finally stayed on barrier precisely.