Research On Implementation Of Public-Key Cryptography Algorithms And Side-Channel Attacks

Over the past years,as an important strategic resource of social development,information plays an increasingly important role in a new round of information revolution and international competition.However,accompanying information security issues also attract people's attention.Ensuring information security is an important factor in safeguarding national stability,promoting economic development and even maintaining world peace.Public-key cryptography is a crucial part in the field of information security,and it is widely applied in many areas including web services,mobile devices,smart card connection,internet payment,etc.Therefore,the research on public-key cryptography and cryptanalysis is of vital importance to social information security,personal data security and even national network security.This thesis focuses on public-key cryptography.Based on basic operation module of public-key cryptography,the author conducts deep and optimizing research on arithmetic operations in finite field which plays a cornerstone role in public-key cryptography.The efficient multiplication algorithm and hardware design on the 2 is proposed for bilinear pairing algorithm based on Pairing Friendly curves' parameter characteristics the classical Montgomery Algorithm.Furthermore,this thesis realizes the classical RSA based on FPGA.After it is transplanted to SASEBO-GII power acquisition development board,the author conducts research on side-channel cryptanalysis.And a practical and feasible power attack scenario combining chosen message and correlation power analysis is proposed after the deep research on chosen message attack and correlation power attack method,which greatly improves the efficiency and accuracy of power attacks.Finally,this thesis study bilinear pairing which is the latest release of identity-based commercial encryption standard SM9.At the same time,this paper uses the computational properties of R-ate cryptographic algorithm,through the hardware implementation of customized based module IP,a SoC system architecture based on Xilinx Virtex-7 series FPGA is proposed to accelerate the speed of the hardware implementation of pairing algorithm.