Power Optimization For A 3D Torus-based Optical NoC Based On Thermal-sensitive Analysis

With more and more processor cores integrated on a single chip,the performance and power consumption of an on-chip interconnection architecture determine those of the whole system.Because of the power efficiency and bandwidth density bottlenecks in traditional electronic interconnects,optical network-on-chip(NoC)is proposed as a new on-chip interconnects technique for its high bandwidth,low cost,and low latency.However,because of thermo-optic effects,extra optical loss resulting from the on-chip temperature gradients during transmitting data packets counteracts the advantages of optical NoCs on power consumption.In order to tackle the problem,we present a thermal-sensitive design and power optimization approach for a 3D torus-based optical NoC.Firstly,for predictable scalability,high integration densities,and low power consumption,we adopt 3D torus topology and hybrid optical-electronic router architecture,in which the 7×7 fully-connected optical switch based on wavelength-selective microresonators helps the optical signals propagate.Secondly,based on an optical thermal effect modeling platform,we propose the thermal-sensitive routing to select the path with the minimum optical loss from all the shortest candidate paths to reduce the extra power consumption.Simulation results show that in an 8x8x2 3D torus-based optical NoC with the proposed routing under several real applications,as compared with an 8x8x2 3D mesh-based optical NoC with dimension-order routing,the power consumption is reduced by 25% if thermal tuning is not utilized.If thermal tuning is utlized,the power consumption is reduced by 19%.If athermal microresonators are used,the power consumption is reduced by 17%.