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Parametric Circuits Optimization With Reinforcement Learning

Posted on:2019-03-22Degree:MasterType:Thesis
Country:ChinaCandidate:C C TangFull Text:PDF
GTID:2428330590951643Subject:Integrated circuit engineering
Abstract/Summary:
In today's integrated circuit design, the topology of many frequently-used building block circuits,such as SRAM cells,logic gates,and typical amplifiers stages,are always fixed and the supply voltage,design target and constraints are different for a specific application.It would be interesting to ask if the design of a class of circuits can be done off-line and be reused in future design.In this paper,this kind of problems is modeled as a parametric optimization,i.e.minθ f(θ,ω),whereθ denotes the design variable and ω parameterizes optimization problem.Since the task of optimization problems is similar to Markov decision process,we adopt reinforcement learning to solve this task.Two networks are trained alternately in continuous space reinforcement learning algorithm.The first network is a policy network,whose output defines the behaviors of the optimizer.The second network is a value network,and it is trained to critic the performance of policy network and to fit the target value function of current policy.The meta train dataset is consist of different functions generated by randomly initializing parameters.An optimizer is trained in the meta train dataset off-line and is tested it in other functions.Experiments demonstrate the effectiveness of the proposed method.
Keywords/Search Tags:reinforcement learning, parametric optimization, circuits optimization, generalization
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