Research On Pedestrian Detection Algorithm Based On ZYNQ System On Chip

With the rapid development of artificial intelligence,an enthusiasm about self-driving,intelligent monitoring and man-machine interaction research is raising.Pedestrian detection technique is widespread concerned on account of its close correlations with the research above.Traditional pedestrian detection algorithms are generally implemented on PC.In recent years,the performance of embedded systems has made great progress,especially the multi-core SoC(System on Chip)of ARM and FPGA.This embedded system has a good many advantages in power,bulk,cost and real-time capability,which promotes the in-depth study and extensive application of pedestrian detection based on SoC.ARM-based SoC is flexible and convenient to develop,but is slow to handle tasks.While FPGA-based SoC has strong parallel computing ability and high processing speed,but has the defect of long development cycle.In terms of the shortcomings above,Xilinx develops an integrated ZYNQ-7000 SoC which combines the superiority of ARM and FPGA.In this paper,a design scheme of pedestrian detection based on ZYNQ SoC is proposed using HOG(Histogram of Oriented Gradients)and AdaBoost(Adaptive Boosting)algorithm fusion on the basis of lucubrating pedestrian detection algorithms and finally implements on ZYNQ-7020.The main research are as follows:(1)Design of pedestrian detection scheme based on SoCThis paper lucubrates the hardware characteristics of ZYNQ platform and then probes into the acceleration technique in the aspect of image processing.Meanwhile,kinds of related feature extraction and classification algorithms are compared concerning algorithm acceleration,resource utilization,detection rate and real-time capability around hardware characteristics.Eventually,a design scheme of HOG+AdaBoost pedestrian detection is proposed based on ZYNQ SoC.In this scheme,algorithms are divided into hardware and software sections adopting HW/SW Co-Design ideal,where complex and time-consuming algorithms are transplanted into FPGA to accelerate,while image reading,result display and control flow are assigned to the flexible ARM.(2)Hardware optimizationIn allusion to the problem of complicated calculation around gradient angles and normalization,an improved method is presented according to the hardware characteristics.The complex computing process is transformed into simple combinatorial logic operation by applying methods of equivalent problem and approximation to optimize the implementation on hardware.As a result,computing speed is greatly improved and resources are effectively reduced.(3)Parallel processing of pedestrian detection algorithm applying pipeline techniqueTraditional design of pedestrian detection algorithm generally employs serial structure which eventually results in poor real-time performance.In order to solve this problem,an optimized hardware structure of pedestrian detection is applied in this paper.The process of HOG feature extraction is divided into several sub-modules which can execute parallelly without buffering the whole image by pipeline technique.As a result,the detection speed is greatly increased while resources are effectively reduced.The experimental results show that the hardware scheme of pedestrian detection proposed in this paper has achieved almost similar detection performance to that of traditional scheme while the former scheme demonstrates a significant improvement in detection speed.Taking a 320 ×240-pixel image as example,ZYNQ approach costs only 17 ms to accomplish the detection which is 9.6 times faster than ARM approach.It is observed that the proposed implementation scheme can perfectly meet the demands of pedestrian detection SoC.