Scalable Coprocessor Architecture Design For Image Target Detection

Image target detection has the characteristics of large amount of data,large amount of calculation and variable processing flow.In the case of high-intensity computational complexity,image target detection and recognition with high accuracy and real-time performance is required.Hardware acceleration is required to improve the calculation speed.The current hardware acceleration architecture is designed according to specific applications.The functions and the processing flow are relatively fixed.When the application environment changes,the circuit needs to be redesigned,what's more,the portability is poor.Aiming at the limitations of the current hardware acceleration architecture,this paper proposes a scalable coprocessor architecture for target detection and a command packet format for implementing this architecture.Enables the microprocessor to simulate the mode of the software function calling to call the hardware acceleration circuit(function IPs module)in the way of writing the command,enabling multi-function IPs to work in parallel.The architecture can change the order of the microprocessor to write the coprocessor command packet and the configuration parameters for working,so that the working mode of each function IP can be configured,the workflow is variable.It is also possible to achieve application portability by accessing different functions and different numbers of IPs on a standard IPs interface.To achieve the scalability of the architecture,multi-IPs parallel work and versatility,a series of key technical issues of the scalable coprocessor architecture are solved.Firstly,the correlation flag datas are added in the command packet format,The scalable coprocessor realizes the detection and control of correlation by parsing the command packet.Secondly,each function IP output bus is separated and a fast arbitration mechanism is implemented to realize high-speed data transmission with functional IP modules working in parallel.In addition,a hierarchical memory structure and a flexible two-dimensional memory address access method are designed to achieve high-speed data access to the memory while meeting the flexibility of target detection for data access.Thirdly,a relatively complete error detection and correction system of the scalable coprocessor,which improves the reliability of the system and provides great convenience for system debugging between software and hardware.Finally,the scalability and functional versatility of the architecture is achieved by constructing a standard IP interface between the functional IP and the scalable coprocessor control components.The circuit design and simulation verification of the scalable coprocessor architecture are completed,and the effectiveness and flexibility of the architecture is verified for the infrared image processing flow on the DSP+FPGA platform.The results show that the scalable coprocessor control unit works at 131.25 MHz,and the shared input bus bandwidth with the function IP reaches 4200 MB/s.When the command packet average length is 512 bytes,the packet processing module parses the data of one packet only.0.975 ?s.The bandwidth of the access memory is also 4200MB/s.It has the advantages of high versatility and high scalability while having low power consumption and small area.