Parallel Large Template Gray-scale Morphological Filtering IP Design

As a nonlinear spatial filtering technique,gray-scale morphological filtering is one of the basic techniques of image preprocessing.It is widely used in image processing systems such as target detection and tracking,and is mainly used to achieve smooth image.Highlight the region of interest in the image,describe the boundary between different regions of the image and other image preprocessing functions^[1].In this paper,we designed a parallel large-template gray-scale morphological filtering IP based on FPGA,which is realized by one-dimensional gray-scale morphological filtering,the size of the structure element can be configured,and the two-dimensional gray-scale morphological filtering with the maximum structure element size of81?81can be realized by calling the IP designed in this paper.The invention reduces the consumption of the storage resources,reduces a large amount of redundant calculation in the filtering process,reduces the consumption of the operation resources,parallel processing of 8 pixels per clock cycle,output data rate is high,can be applied to an embedded image processing system with high real-time requirements and limited hardware resources.In order to reduce the storage resource consumption in IP implementation,a two-dimensional morphological filter based on one-dimensional morphological filter is designed to reduce the storage resource consumption caused by two-dimensional window generation in large template filtering.The data analysis mode of one-dimensional morphological filter column operation is required.A column transposition circuit is designed to provide eight adjacent column pixels per periodic image operation circuit.In view of the problem that IP must improve the clock working frequency to meet the real-time requirements of the system,the parallelism of morphological filtering is fully developed by mining the reusability of operation circuits in the process of morphological filtering with large templates.When IP is configured with different structural elements,the extreme value operation circuits are the same and share a 74 input extreme value circuit,which reduces the consumption of operation resources and improves the data pass rate of gray morphology filter IP.Meet the real-time requirements of the system.According to the above scheme,the design of parallel large template gray-scale morphological filtering IP circuit,functional verification,synthesis,layout and routing are completed in this paper.The logical synthesis and implemetation of IP is carried out on XC7K325T-I model FPGA of Xilinx Company.When the maximum clock frequency is150MHz,transfered IP to do one-dimensional gray-scal morphological erosion or dilation of image which size is512?64 0,the time consuming is about 0.33ms,the output data rate is achieved 984Mpx/s,when the two-dimensional gray-scale morphological erosion or dilation is realized.The time consuming is about 0.99ms,the output data rate is328Mpx/s,when the two-dimensional gray morphology open or closed operation is done,the time consuming is about 1.32ms,the output data rate is 246Mpx/s.Consume less computing and storage resources can meet the real-time requirements of embedded image processing system.