Research And Implentation Of Residual Network Based On FPGA

In recent years,convolutional neural networks(CNN)have been used in various application fields such as image classification and attitude estimation with excellent performance.They are very suitable for unmanned aerial vehicles and unmanned driving scenarios.However,as the most common deep learning platform,GPU has some limitations in power consumption due to its poor energy efficiency ratio.So it cannot meet the requirements of some embedded low-power platforms.This leads to the limitation of its practical application.Embedded CNN needs some implementation methods with less resource requirement and higher efficiency.This thesis focuses on how to efficiently implement deep convolution neural network on the platform of FPGA.With the increase of network depth,there will be over-fitting problem in plain networks.The residual network can address this problem effectively and it has achieved good results in many applications.Therefore,this thesis chooses residual network architecture among many neural network architectures.According to the different ways to implement the shortcut connection,a 30-layer residual network which implements the shortcut connection in zero-padding mode is finally selected to be implemented on the FPGA.According to the characteristics of FPGA hardware platform and the selected network,the overall design of the circuit and the design of each sub-module is carried out in this thesis.There are large amount of weights and input/output data of each layer of the selected network,so DDR is needed to store the data.In this thesis,Xilinx MIG IP core is used in the process of reading and writing DDR to avoid the complex direct operation of DDR.According to the structure and operation process of the selected residual network,this thesis designs the forward reasoning part of the network.In the selected network,the fully connected layer and maximum pooling layer appears only once,while the residual block structure appears many times.In this thesis,the reuse of computing units between different residual blocks is fully considered in the design.In addition,because the global pooling in the network is similar to the pooling operation on the shortcut connection,computing resource between them are also reused to save hardware resources.In the forward reasoning process of the selected residual network,3×3 convolution accounts for the vast majority.Therefore,in this thesis,3×3 convolution operations are fully expanded in the processing element module to accelerate the network.Because of the large number of parameters of the selected network and the frequent use of each parameter in the process of operation,this thesis adopts on-chip caching strategy to reduce the time on data fetching.Weights and bias parameters of single layer of the network are read from DDR each time,and are stored in the on-chip BRAM.And we maximize on-chip data reuse,avoid repeated access to off-chip storage.Experiments are carried out to evaluate our design,outputs of our design are compared with results from the software implementation.The comparison results show that the designed system has the advantages of low energy consumption and less resource consumption with correct function.So it can meet the application conditions of general embedded low power platform.The design of the FPGA circuit based on the residual network architecture has partial universality.After approprite modification,our design can be extended to other networks with similar structure,which has practical significance.