Design Of Convolutional Neural Network Hand Gesture Recognition System Based On FPGA

Hand Gesture recognition is becoming more and more popular as a more natural and flexible way of human-computer interaction.The traditional hand gesture recognition method mainly relies on mathematics and image processing technology,and the recognition rate is low and the robustness is poor.At present,researchers use deep learning algorithms for hand gesture recognition.The algorithm has translation and rotation invariance for images,and has low impact on illumination,so it has high recognition rate and good robustness.However,the algorithm is computationally intensive and has poor real-time performance.The problem of platform size and its high power consumption when using GPU(Graphics Processing Unit)for acceleration and the problem of high cost when using ASIC(Application Specific Integrated Circuit)platform for acceleration limit the algorithm's usage in embedded mobile platforms.When taking those problems into consideration,we plan to design a real-time hand gesture recognition system integrated in FPGA to realize a real-time hand gesture recognition.In response to the computationally intensive features of convolutional neural networks,we firstly analyze the time complexity and spatial complexity of convolutional neural networks in this paper.Through the above analysis,by simplifying and optimizing the existing network models,we design a convolutional neural network model,which can be implemented on FPGA platform.In this model,we omit the pooling operations in the convolutional layer.After analyzing the positive correlation between the output layer and the softmax layer output,the softmax layer of the network is omitted,and the input is attributed to the class represented by the largest value in the output layer by comparing the value of the output layer.Then,the GPU is used to train the network on the PC side.After the training is completed,the model parameters are extracted for the pre-term reasoning of the convolutional neural network on the FPGA.In response to real-time problem of convolutional neural networks,we make full use of the detailed analysis of convolutional neural network algorithms to fully mining the potential parallel computing possibilities in convolutional neural networks in this paper.These parallelism are the parallelism between the image local perceptual domain and the convolution kernel for convolution;the parallelism between different feature maps and convolution kernels;and the parallelism between different layers in the network structure.In combination with the FPGA situation,we propose to accelerate the matrix convolution operation in a fully-expanded manner;accelerate the parallelism between different convolution kernels by using PIPELINE,a kind of pseudo-parallelism calculation manner;accelerate the parallelism between different layers by using same module.Since the number of neurons in the fully connected layer is constant,in the process of preinference of the network on the FPGA,the 1080 p image acquired by the camera must be scaled before being used as the input of the network.In order to ensure that as much information as possible is preserved during image reduction,we use bilinear interpolation algorithm to scale the image in this paper.Finally,the Network is implemented on the Xilinx Zynq-7000 SoC processor.Experiments show that the FPGA can accelerate the convolutional neural network and improve the real-time performance of the network.