Research On The Key Technology Of Massive MIMO Detection Architecture In Reconfigurable Computing Chip

As the continual of economic development,people have a requirement for mobile Internet,which is trending much more diversified.In the future,mobile communications with several new technologies such as big data,cloud computing,artificial intelligence will accelerate the arrival of the gold age of information in the next 10 years.All those emerging services have put forward higher requirements for both real-time computing ability and communication transmission.In order to satisfy the requirements of future wireless communication transmission as well as low power consumption,massive MIMO signal detection chips need to achieve low delay,high throughput,high energy efficiency as well as to satisfy a certain degree of flexibility and extensibilit y requirements.Based on all those problems above,this paper focuses on the operator level of hardware structure and proposes a solution to optimize the operation efficiency of processor.In this scheme,a reasonable coarse-grained abstraction of the signal-detection algorithms is adopted by hardening logic on the operator level.There are 3 advantages of using this scheme in massive MIMO detection reconfigurable processors: 1.High flexibility and scalability: supporting a variety of signal detection algorithms and different channel size flexible configuration.2.Reduction in configuration information number: Evaluating by the same algorithm,the configuration information number is only 1/3 of the GReP.Besides,the configuration packet switching speed is faster,and the transmission error rate can also be reduced.3.The mixed granularity is contributed to dispatch of upper level: providing more operations to compiler,which makes the compiler more probability to optimize.Then,an optimization strategy is proposed to improve the data processing speed of the massive MIMO detection reconfigurable processor.Aiming at the problem of the data-exchange efficiency of the computing array and on-chip storage,the data circulation pattern with ping-pong buffer is designed,which defuse the conflict between high processing speed and limited on-chip storage when it comes to large scale complex data processing scenario.Last but not least,a critical path optimization strategy is proposed for the processing unit of massive MIMO detection.A probabilistic truncation multiplication algorithm is proposed in imprecise computation filed,which estimate the influence of the truncated part and adding to with the exact computing part.Compared to DC synthesis tool base multiplier,simulation shows that it pays only 1.6358 points of precision loss,in return at least 2% reduction in delay,at least 11% area reduction,and at least 36% power consumption reduction.The massive MIMO reconfigurable detection processor proposed in t his paper can achieve the dominant frequency of 800 MHz under the TSMC 28 nm and voltage of 0.9V,the size of which is 4M Gates.After the evaluation of 9 algorithms such as Matrix Inv(8×8),HBF,FIR,under the condition of serial processing(with all hitting in the first-level cache and data stored in the assumed format),the theoretical energy efficiency ratio of proposed processor is 7.49 to 12.87 times higher than that of TI C66 x DSP processor.