Research And Implementation Of Binocular Stereo Matching System Based On FPGA

The binocular stereo matching algorithm has a wide range of applications in computer vision,and the development trend is toward a mobile embedded platform with high precision,low latency and low power consumption.In view of the fact that the existing general-purpose processing platform can't reach the performance index of the embedded platform,this paper carries out research and implementation of the binocular matching system on the embedded platform.This article uses an embedded SoC hardware development platform based on the Xilinx Zynq-7020 FPGA chip,which integrates Cortex-A9 ARM and programmable logic unit.In this paper,based on the hardware platform characteristics,the binocular matching algorithm is studied and analyzed in detail.The main work content includes the following three aspects:The first is the choice of key algorithms.The Mini-census algorithm requires less hardware implementation resources than the Census,and the accuracy of the two is equivalent.Sometimes the accuracy of the former is even better than the latter,so the former is adopted for initial cost calculation in this paper.After the adaptive region is constructed for the image,the initial cost is aggregated.Compared with the cost aggregation method without constructing the adaptive region,the accuracy is greatly improved.Therefore,this paper adopts a method with the adaptive region.The second is the selection of adaptive regions.In this paper,the selection of the adaptive region is compared and analyzed.The method of constructing the adaptive region only for matching pictures is better than the method of taking the intersection of constructing the adaptive region for adaptive regions and candidate images.Moreover,the former reduces the normalization operation and hardware computing resources compared to the latter.Therefore,this paper uses the former to carry out cost aggregation,saving hardware implementation resources without reducing accuracy.Finally,hardware acceleration.Taking advantage of the characteristics of SoC in the FPGA device,the depth calculation in this paper chooses to perform custom acceleration in the programmable logic part.Among them,the cost calculation realizes the parallel computing of the pipeline by setting the calculation buffer and preparing buffer;the cost aggregation adopts the vertical and horizontal aggregation mode,and the horizontal aggregation buffer realizes the fast calculation by using the pipeline operation.After the final parallax is obtained,the result is output to the off-chip memory through the interaction between the ARM and the programmable logic.This paper implements a binocular stereo matching algorithm test system based on the aforementioned embedded hardware development platform.In the system performance test,the SD card is used to complete the image input and the output of the parallax result,thereby achieving performance analysis.In this paper,different picture resolutions are tested under different parallaxes at the system clock frequency of 100 MHz.The results show that the processing speed is three orders of magnitude higher than the Intel Pentium 4 processor operating at 3 GHz;and the system power consumption is below 2 W,meeting the performance requirements of embedded platform deployment.