Design And Implementation Of Parallel Algorithm For Real-Time Digital Coherent Optical Receiver Based On FPGA

With the increasing demand for greater bandwidth and longer distance in society,the role of digital coherent optical communication technology in the field of optical communication has become more and more prominent,and its weight has become larger and larger,and it has gradually become the key technology in the next generation of optical communication.In the field of digital coherent optical communication technology,it needs to be implemented by DSP related algorithms.At present,related algorithms mainly rely on offline algorithms in this field,but parallel real-time algorithms can better meet the needs of high-speed processing.This paper is mainly about the parallelization of IQ orthogonal unbalance compensation algorithm and phase compensation algorithm in digital coherent optical communication and its implementation on FPGA development board.The main research contents of this paper include:(1)The related algorithms in digital coherent optical communication are introduced in detail.The composition of QPSK system platform and the flow of digital coherent optical communication are introduced.The experimental platform of QPSK coherent optical communication system is built.(2)Use MATLAB to carry out serial research on orthogonal unbalance compensation algorithm and phase compensation algorithm,select better parallel number by calculating experimental data,and then obtain BER curve and performance analysis under different attenuation conditions.According to the optimal number of parallel paths obtained in the offline algorithm,the parallelization code is written in Verilog language on Quartus,and the experimental data is input into Quartus,and the calculation result is observed by modulesim,so that the parallelization of related algorithms is realized in Verilog language.(3)Set up the experimental platform of QPSK coherent optical communication system,and write the parallelization code successfully debugged on the Quartus software to the FPGA development board.The real-time signal of the related algorithm is calculated on the FPGA by transmitting the real-time data sent by the coherent receiver in the experimental platform to the FPGA.Use signaltap to capture real-time data,draw constellation diagrams on MATLAB and calculate the bit error rate to achieve parallelization of related algorithms.