Research And Design Of A Control Circuit For PIR Based On SAR ADC

The pyroelectric infrared sensor detect the human body by absorbing infrared radiation at a specific wavelength and converting it into a weak electrical signal.The traditional pyroelectric infrared control chip amplifies and filters the input weak electric signal,and then input to a dual-threshold voltage comparator for comparison,and then outputs the comparison result.The logic circuit judges whether to output the effective driving signal according to the comparison result.This thesis designs a pyroelectric infrared control chip based on successive approximation analog-to-digital converter.The pyroelectric infrared sensor control chip designed in this thesis replaces the dual-threshold voltage comparator with an analog-to-digital converter and a digital comparator.Digital signal processing circuit replaces analog signal processing circuit to reduce chip false alarm rate.An LDO with a high PSRR is designed inside the chip to power the internal modules of the chip and external sensors.LDO uses nested Miller compensation to ensure stable operation under full load conditions.The differential slew rate enhancement circuit is added outside the main loop of the LDO.The main loop needs some time to adjust when the load changes This circuit provides the charge and discharge path to the parasitic capacitance of the gate of the power transistor,and improves transients responding speed.A relaxation oscillator with an oscillation frequency of 1MHz is integrated inside the chip to provide a clock signal to the ADC.The amplifier for amplifying the weak electrical signal is composed of a plurality of fully differential operational amplifier cascades to reduce the distortion of the signal.Analog signal input to successive approximation analog to digital converter and converted into digital signal.The sampling circuit of the analog-todigital converter uses a capacitive lower plate sampling technique to avoid charge injection effects and clock feed-through.The DAC converter uses a resistor-capacitor hybrid structure.A high-order 7-bit sub-DAC consists of a charge-transfer DAC.The lower 5-bit sub-DAC consists of a resistor divider type.Comparator consists of preamplifier and latchThe chip is designed in a 0.35?m BCD process and verified by Cadence IC5141.Simulation results show that the LDO's low-frequency power supply rejection Ratio is-78 d B,and the power supply rejection Ratio reaches a worst-case value of-45 d B at a frequency of 39.8KHz.When the LDO load transitions from 0m A to 15 m A,the output voltage changes to 290 m Vand the output recovery time is 61?s.When the load current changes from 15 m A to 0m A,the output voltage changes to 128 m V and the output recovery time is 47?s.The SAR ADC ENOB exceeds 10 bits,achieving the expected accuracy requirement.The chip function is normal and the performance meets the design requirements...