A Hardware Solution For Image Super Resolution Based On Edge Directed Interpolation Algorithm

Image super-resolution reconstruction technology can effectively improve the image quality and greatly enhance the information in the image.With the popularization of mobiles and the high demand of image quality,it is significant to propose a solution to accelerate the super resolution process both on software and hardware.The interpolation-based algorithm can be easily ported to hardware platforms since its simple work flow and low computation.Consequently,a hardware accelerator for edge-directed interpolation algorithm is proposed in this thesis.It can reduce the multiplication by two-third to use some registers to store the results of last two matrix multiplication used in the interpolation algorithm.Furthermore,Cholesky decomposition algorithm is proposed to simplify the matrix inversion involved in the interpolation algorithm,which reduces the multiplication and storage space by nearly half compared with the LU decomposition algorithm.An optimized Goldschmidt algorithm is proposed to design a fixed-point divider to accelerate the division in Cholesky decomposition algorithm.Firstly,the input data can be easily scaled by shifting the value according to the first bit where one appears.Then the scaled value is once more amplified by piecewise linear fitting.Finally the quotient could be obtained after twice iterations on dividend according to basic Goldschmidt algorithm.Besides,in this thesis a combination of coarse and fine grained flow control scheme is used to reduce the bubbles and improve the resource utilization and data throughput.The divider and multiplier are designed as a 4-level pipeline structure to improve the throughput.Moreover,the division and multiplication in the algorithm are scheduled properly so that it can perform two process of matrix decomposition inversion simultaneously by using the same hardware units.Experiments show that the frequency of the designed fixed-point divider reaches 198.5MHz,and the time delay for one division is 30.752ns.The data throughput of the divider is about 198.5Mdiv/s,and the maximum error is only 0.00448%.The frequency of the Cholesky decomposition inversion module is almost 181MHz,and its maximum error is about 4.7515%.Also,the whole hardware implementation can run at the frequency of 181 MHz,and the output data can be obtained every 14 clock cycles.About 97.8%value of the output data can be directly used as the pixel in high resolution image while the tolerable absolute error is less than 1.