Research And FPGA Implementation Of Two-Dimensional Wiener Filtering Algorithm For NGB-W Channel Estimation

With the increasing demand for broadcast network and the great developing of communication technology,the "triple play" among broadcast television network,telecommunication network and the internet is the inevitable trend of the development of electronic information technology.NGB-W(Next Generation Broadcast-Wireless)system is a vital part of the next generation of broadcast television network.It has the ability of triple play,manageable and controllable,ultra-high-speed bandwidth,and two-way interactive architecture,and at the same time promotes the rapid development of the next generation of broadcast television network.As a key of the whole wireless system,wireless channel has a fatal impact on the performance of the whole system.Meanwhile,the performance of the channel estimation is directly related to the performance of the receiver.At present,the NGB-W system mainly uses OFDM(orthogonal frequency division multiplexing)technology to estimate the channel,but it still lacks the hardware development of the system prototype.Therefore,for the NGB-W system,the research of channel estimation technology based on FPGA can not only verify the existing algorithm model,but also play an important role in the further development of system prototype.This paper is aimed at the research of FPGA implementation of channel estimation algorithm for NGB-W system.The main contents are as follows:(1)Firstly,giving the outline of the background and significance of the NGB-W system,the importance of channel estimation to the NGB-W system is also declared.Then introducing some related knowledge of the NGB-W system,including the introduction of the NGB-W system and the OFDM transmission technology.Finally,we further introduce and analyze the channel propagation characteristics of NGB-W broadcast wireless network,which lays the foundation for the following chapters.(2)We have studied the current channel estimation algorithm.Above all,we introduce the pilot and describe the structure of pilot used in the current NGB-W system.Then we describe two pilot-symbol-aided channel estimation algorithms,and compare the advantages and disadvantages of the LS(Least Squares)algorithm and the MMSE(MinimumMean Square Error)algorithm.Then three main interpolation algorithms areintroduced: linear interpolation,high order interpolation and wiener filtering interpolation.Finally we focus on two times one-dimension wiener filtering algorithm,which the current NGB-W system adopted,and simulate with CCSS simulation platform.We compare the performance between the two times one-dimension wiener filter algorithm and linear interpolation algorithm,and the simulation results show that the performance of the two times one-dimension wiener filtering algorithm is better than that of the linear interpolation algorithm and meet the requirements of NGB-W system.(3)We refer to the known two times one-dimension wiener filter channel estimation algorithm to analyze the implementation of specific hardware algorithm.Firstly,the algorithm is on fixed-point analysis to determine the fixed-point standard of the algorithm.Secondly,splitting algorithm.The actual algorithm is divided into LS estimation algorithm,time domain interpolation algorithm and frequency domain interpolation algorithm.And then analysing the implementation of hardware,writing code respectively.Finally,the implementation of each part of the algorithm is integrated,and using Modelsim for logical simulation,then the source code that meets the requirements of the actual design is obtained.Afterwards,making the test on the FPGA board.After finishing the compilation and synthesis with Quartus II,the file is downloaded into the FPGA board,and the results are compared with the results of the floating point algorithm obtained by the CCSS simulation platform.The final contrast results meet the requirements of the NGB-W system and the maximum working frequency can reach 126 MHz,and can support PP1?PP5,2K/4K/8K/16 K patterns at the same time,which confirms the correctness of the whole channel estimation hardware design.