Runtime Analysis And Verification Of System-on-Chip Simulation Traces

Along with the rising of Cyber Physical System,System-on-Chip(SoC)plays an important role in the industry.During the development cycle of SoC related hardware/software systems,developers usually use Virtual Prototyping technique to model and test their systems upon SoC simulators,in order to ensure that system designs meet some constraints.Simulators during their execution usually generate simulation traces that record the track of state changes.These traces are usually dumped into huge log files.When engineers need to analyze properties of their system,they often need to check the log files and manually analyze traces.However,the huge size and extra verbose information make it nearly impossible to manually analyze traces,even with the help of regular expression tools.Based on this,the Trace Runtime Analysis Platform(TRAP)is designed to help verify simulation traces.TRAP provides a model-based framework and corresponding tool chain to support automatic runtime analysis of traces.The main goal is to make it easy for engineers to define system properties that should be satisfied and verify them at runtime(or from a recorded trace file).TRAP takes Clock Constraint Specification Language(CCSL)as its theory basis.Engineers firstly itemize simulation traces and map these information blocks into logical clocks,next define system properties,then use C++ code generated by TRAP to compile the verifier,finally run the verifier together with simulator simultaneously and verify the properties.TRAP uses Eclipse Modeling Framework(EMF)to design several Domain Specific Languages(DSLs).User uses these DSLs to interact with each part without the need of knowing underlying implementation or theory.The whole tool chain is loosely coupled and can be applied to different simulators,which allows several engineers to work on different parts simultaneously.Experiments shows that TRAP can verify traces in very short time and help engineers find bugs in system design.