Design Of Signal Acquisition And Communication Control Chip For Speech Wireless Detection

Due to special needs,people use eavesdropping method to investigate cases and acquire information in the field of military and public security.The wireless signal for eavesdropping is speech signal,which is acquired and sent by eavesdropping device and received by receiving equipment in the RF coverage area.The signal acquisition,processing and transmission are very important for the whole process.The speech signal should be converted into digital signal first.Because of the characteristics of speech signal,it needs to be compressed and added some redundancy before transmission to improve the effectiveness and reliability of communication.Meanwhile,the eavesdropping device will be hidden for a long time,so the size,power consumption and delay should be considered during the circuit design stage.The main work in this thesis is to design a signal acquisition and communication control chip in wireless speech acquisition system.This chip is specially used in eavesdropping devices.It contains control circuit,transmitter baseband circuit,compression encoder and auxiliary circuit.The circuit implementation is optimized due to the small-size and low-power applications.The control circuit manages the entire sleeping,transmitting and receiving processes,ensuring the whole chip work correctly.The transmitter baseband implements channel coding,packing and modulation functions.The modulation method is MSK.Considering low power and real-time requirements,a self-defined communication protocol is presented in this thesis,so that the transmitter works intermittently to reduce the power consumption and the time delay.The compression encoder uses G.726 speech coding algorithm which is defined by International Telecommunication Union(ITU).By optimizing hardware implementation,the G.726 compression algorithm can compress 16 ksps,16 bit speech signal into 4 bit code word while ensuring speech quality at the same time.Also,because G.726algorithm is a kind of lossy compression algorithm,the data will be degraded,and the quality of compressed signal can not be evaluated directly.Therefore,based on human auditory model,this thesis uses perceptual evaluation of speech quality(PESQ)algorithm to evaluate the quality of encoder and ensure the compression performance.The auxiliary circuit consists of decimation filter and I2S interface.For decimation filter,it is a part of Sigma-delta ADC.The decimation filter consists of cascaded integrator comb(CIC)filter and half band filter,using hardware reuse technique to reduce circuit area.And the I2S interface is a parallel to series data converting circuit,which is used for data output.The thesis introduces the simulation and hardware realization process of above circuit in detail,and gives simulation results,finally verifies in FPGA.The circuit in this project is implemented in UMC 0.18?m CMOS process with a1.8 V supply voltage and a 24 MHz clock,and the chip is still in production stage.As for transmitter baseband circuit,the circuit area is 0.4 mm~2 and the power consumption is 0.5 mW.The data rate of transmitter can adjust.Because the transmitter works intermittently,it can reduce about 30%power consumption in RF circuit.The G.726speech coder can support the bit rate of 32,24 or 16 kbps.It is verified by PESQ algorithm and the simulation results show that it can achieve a MOS-LQO of 4.1,which meets the application requirements.