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Research And Development Of An Algorithm About Face Recognition Based On FPGA

Posted on:2019-04-26Degree:MasterType:Thesis
Country:ChinaCandidate:Y LiuFull Text:PDF
GTID:2428330563992280Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
With the popularity of mobile devices and the rise of smart homes,the need for convenient authentication methods and search methods for face recognition has become more urgent.The face recognition methods used by Alipay based on software.The application of various scenes is not rigidly adhered to software,such as the security inspection at the railway station,and the speed needed to rely on hardware is improved.In the process of hardware implementation,the face recognition algorithm will encounter many problems caused by the face data,which will lead to excessive consumption of resources,long operation time,and so on,which brings a certain degree of difficulty to the implementation process.The sparse expression algorithm uses the projection principle of the matrix to simplify the data.This paper proposes a new concept of "difference between classes".Compared with the DSNPE algorithm.After the simulation in MATLAB,the improved algorithm perfectly increased the recognition time keeping the rate.The recognition rate can be maintained at 80%,90%,and 80% on the YALE,ORL,and AR face databases,respectively,and the recognition time can be reduced by 40% to 60%.Hardware circuits are designed for some of the algorithms.The sub-modules are designed with reference to singular value decomposition,bilateral Jacobian algorithm and CORDIC algorithm.This paper improves the implementation of CORDIC in place of the stream structure with an iterative structure,and saves the use of resources.The basic calculation unit contains 4 sub-modules: division module,inverse tangent module,sine cosine module and bilateral rotation module.After the design of the circuit,this article uses ModelSim software and FPGA development board to build the simulation environment.We uses ModelSim to verify function and uses FPGA to realize the circuit.The maximum clock frequency of the entire basic computing module is 262.854 MHz,and the resources occupied are 1418 Slice registers,4080 Slice LUTs.
Keywords/Search Tags:Face recognition, sparse representation, SVD algorithm, bilateral Jacobi algorithm, CORDIC algorithm, FPGA
PDF Full Text Request
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