Research On The Packets Processing Acceleration Technology For Virtual Network Function

By now,with the rapidly expanding of the network scale and the increasing in types of network functions,the network operators who use the traditional dedicated network facilities are faced with the difficults of the fierce increasing in the cost of network construction operation and maintence,the slow deployment of new functions and the long cycle of development.To solve these problems,the Network Function Virtualization(NFV)architecture has been put forward.Virtualization technology is utilized to implement the hardware resource-pooling,and managed and scheduled uniformly as virtual resources.Virtual Network Function(VNF)is an important part of NFV architecture.It is a software-based network function which can implement the decoupling between network functions and specific hardware devices and improve the flexibility and scability of network.However,because of the low performance of software,the throughput of VNF cannot achieve the standard of quality of service(QoS),which hinders the innovation and deployment of network functions.Therefore,we need design a common hardware acceleration architecture to improve the performance of data processing for VNF as well as keep the flexibility of network.Supproted by the National Basic Research Program of China(2013CB329104)— "Network Components Model and Clustering Mechanism”,this dissertation concentrates on the research of NFV packets processing acceleration technologies.Common hardware acceleration architecture design,stateful VNF acceleration architecture and the deployment of accelerators in NFV data cemter and dynamic acceleration resource scheduling policy are studied.The main innovations of this dissertation are shown as follows:(1)To improve the data processing performance of stateless VNF,a Function Adaptive Resource Dividable(FARD)hardware acceleration structure is presented.Firstly,we implement the reconfiguration of protocols with programmable parser,which supports the parsing of different types of packets and implements the function-adaptivity of accelerator.Secondly,with the dividable match table(DMT),which ensures the isolation among different acelerators and decreases the resource cost of the accelerators.Finally,the allocation of storage resource is optimized by the resource division optimization algorithm.Compared with the software-based VNF,the design in this dissertation can increase the throughput of VNF by 60.2 times,and the resource cost optimization rate can reach 36.6% on average.(2)In order to solve the problem that the effect of stateless hardware accelerator is not ideal for stateful VNFs,a Stateful Function Processing Acceleration(SFPA)structure is proposed to improve the pipeline of current data plane to support the stateful information processing.The structure implements the acceleration for stateful VNFs effectively and decreases the resource cost with the resource allocation optimization algorithm.The throughput of VNF which is accelerated by SFPA is 2.9 times higher than which is accelerated by DPDK,and 1.7 times higher than the stateless hardware accelerator.The resource cost optimization rate can reach 41.9% on average with the resource allocation optimization algorithm.(3)A hardware acceleration platform(HAP)is designed for NFV data center.The HAP adopts the dynamic partial reconfiguration FPGA to implement the flexible deployment and effective management for common acceleration architecture and utilizes the genetic algorithm-based dynamic acceleration resource scheduling policy to improve the sum acceleration profit with limited acceleration resource by 10.4% approximately.