An Acceleration Platform For Face Detection And Recognition Based On FPGA

With the emergence of new and emerging technologies,traditional authentication methods such as passwords and swipes have security holes.Different people have different biometric characteristics such as retina,iris,fingerprint,and human face.Therefore,biometric information can be used for authentication and identification.As a basic human biometric information,human face has the advantages of simplicity,speed,convenience,and so on in the realization of personal identification.Face detection refers to determining whether there is a face part in a picture through an algorithm,and if the face part is included,the coordinate position of the face in the picture is output.Face recognition refers to judging the identity of a person's face from a face picture that has already been acquired.In the process of face detection and recognition,more computing resources and computing time are required.In some specific scenarios,especially in embedded devices,the serial computing mode of a Central Processing Unit(CPU)is difficult Meet the real-time detection and recognition requirements of human faces.Therefore,it is very important and urgent to explore the heterogeneous computing platform to accelerate face detection and recognition.The Field-Programmable Gate Array(FPGA)has better concurrency than the CPU's calculation mode.The storage unit and the computing unit in the FPGA are nested within each other.According to the computational characteristics of the algorithm,the algorithm can be designed to meet the computational characteristics of the algorithm.The hardware structure improves the parallelism and throughput of the algorithm and reduces the running time.On the basis of analyzing and summarizing face detection and recognition algorithms,this paper uses heterogeneous platform technology based on CPU and FPGA to try to explore the process of accelerating face detection and recognition.In the face detection process,this paper uses the method of concurrency and pipeline to accelerate the Viola-Jones face detector algorithm.The concurrency part is mainly designed in the first five stages of the cascade classifier in the Viola-Jones face detector algorithm to increase the data throughput.And increase the degree of parallelism of cascaded classifiers.Due to the limitations of the FPGA's own resources,the latter 20 stages of the Cascaded Classifier in the Viola-Jones face detector algorithm use the pipeline acceleration method in order to increase the throughput of the algorithm data as much as possible.In the process of face recognition,this paper uses Convolutional Neural Network(CNN)as a face classifier.The face detection algorithm passes the obtained face image to the convolutional neural network by the convolutional neural network.Judging its category.The accelerating process of the convolutional neural network is realized by the method of concurrent convolution operation and pipeline feature map.The face detection and acceleration platform studied in this paper is developed using XILINX's VIVADO HLS.VIVADO HLS contains a large number of parallel optimization instructions,which can speed up the development of FPGA programs and reduce the complexity of verification work.VIVADO HLS can convert C code into C code.The Register Transfer Level(RTL)circuit greatly improves the efficiency of FPGA program development.This paper uses the PCIE protocol as the protocol for the communication between the PC host and the FPGA in the heterogeneous platform.The PCIE driver uses the XILLYBUS open source driver.This paper accelerates the face detection process by accelerating the Viola-Jones face detector algorithm and accelerates the face recognition process by accelerating the convolutional neural network.The experimental FPGA development board is XILINX's KCU105 development board.The compiler used is VIVADO HLS and VIVADO.The parallel optimization instruction in the VIVADO HLS converts the C language code to Verilog code and encapsulates it as(Intellectual Property)IP core in VIVADO.The packaged face detection IP core and PCIE IP core are assembled.After compilation,synthesis and implementation,the bitstream file is obtained.The bitstream is downloaded to the FPGA development board to implement the layout and routing of the FPGA internal resources.The experimental results verify the acceleration effect of the heterogeneous computing platform studied in this paper.Under 320×240 pixel video real-time transmission,the hardware platform's processing capability per second reaches 21.8 frames.Compared with the software detection and recognition platform,the acceleration rate of the hardware platform reaches 2.9X.