The Dielectric Properties Of TiO₂ Ceramics Annealed In Reduced Atmosphere

With the development of modern microelectronic technology,microelectronic devices are becoming more miniaturized and integrated.In the microelectronic devices,dynamic random access memory?DRAM?has wide application prospects in actual production,and one of the core technologies of DRAM is materials with colossal permittivity?CP?,which possessed colossal dielectric permittivity?>10⁴?as well as low dielectric loss?<0.05?.In recent years,the research on CP materials has been a hot research direction in the electronics industry,CaCu₃Ti₄O₁₂?CCTO?is one of the popular CP materials,because it's high dielectric constant,usually in the order of 10⁴.However,it is difficult to get a low dielectric loss.A high-performance dielectric material should exhibit temperature-and frequency-stable,high permittivity as well as low dielectric loss(<10^-1).Nevertheless,achieving CP meanwhile getting low dielectric loss in a single material is still an extremely challenging task,comparatively,the latter is far harder than the former.Nowadays,several mechanisms used to explain colossal permittivity?CP>10³?have been proposed,such as barrier layer capacitance?BLC?,nano-scale disorder,Mott-variable-range-hopping?Mott-VRH?,electron-pinned defect-dipole,etc.As we know,there is another mechanism relating to thermally activated carrier hopping associated with substitutional defect states could lead to CP,If these carriers hopping can be replaced by localized lattice defect states,a CP,an acceptable dielectric loss and a less frequency/temperature dependence can be obtained simultaneously.Unfortunately,the charges polarized by an external electric field usually participate in the conduction process of external circuits,leading to large leakage losses.It is conceivable that if carrier hopping could be confined/localized in the material,getting both CP and low dielectric loss will be more easily.Based on this,we have made some related research and discussion in this artcle.In this work,pure TiO₂ ceramics were prepared by the conventional solid-state sintering and the optimized sintering condition is 1400 ^oC in air for 10 h.Then,TiO₂ceramics were annealed at 1150 ^oC in Ar?with 0.1%H₂?for 5 h.We measured the maximum dielectric permittivity?².7×10⁴?obtained in TiO₂ ceramic with the measured dielectric losses below 0.07?100-10⁶Hz?.According to the analysis of sample's microstructure,element valence,the resistivity of surface and internal,different temperature of dielectric properties,we found that the surface resistivity is more than 10⁹?·cm?upper limit of our instrument?at room temperature,which is conflicting with the universal acknowledge reported in many documents.However,the internal resistivity of the annealed TiO₂ ceramics is 91?·cm.The XPS shows that a great number of carrier concentrations due to oxygen vacancies in the TiO₂ ceramics.Accodring to the color change of samples observed in the experiment,we consider that in the surface of TiO₂ceramic,there are a great amount of H₂O molecules and OH groups,one oxygen vacancy can fill two OH groups to form dimerics.When all of free electrons from the oxygen vacancies are restrained by OH groups by the covalent bond,an insulting layer is presented in the surface of annealed TiO₂ ceramic.However,the oxygen vacancies in the inner of the simple can not get in touch with OH groups,so the internal resistivity of the annealed TiO₂ceramics is very low.Therefore,it is suggested that the CP is attributed to the large carrier concentration of the semiconductor,while the low dielectric loss is due to the existence of the insulator layer on the surface.According to this mechanism,we designed the insulator/semiconductor/insulator?ISI?structures with three different materials.Firstly,we measured the dielectric properties of single-crystalline silicon plates after thermal oxidation.It is exciting that the dielectric properties measured at room temperature is nearly up to the order of¹0⁴ with the loss below 0.05?100-10⁶Hz?because of the surface SiO₂ insulators.Secondly,it is also surprising that the dielectric properties of the n-type silicon plates with top and bottom Ga₂O₃ layers deposited by PLD method are similar to those of the TiO₂ ceramics annealed in 0.1%H₂/Ar.Finally,the Al₂O₃/TiO₂/Al₂O₃ three layers were deposited on the Pt/Ti/SiO₂/Si substrate by PLD.The dielectric constant is about 2000 at room temperature,which is ten times higher than that of pure TiO₂?nearly 180?,while the loss is kept below10%at the frequency of 10³-10⁶Hz.In conclusion,a semiconductor with a large carrier concentration and an insulator layer can achieve CP and low dielectric loss simultaneously.