Spike Neural Networks Hardware Implementation Research Based On FPGA

The rapid development of neuroscience has accumulated a lot of knowledge about the structure and function of human brain.The research shows that the brain is composed of dense and complex neurons and exhibits many surprising properties(e.g.pattern recognition,decision making etc.).The biological neurons transmit information and perform computations through the timing of spikes.The computational model of Spiking Neural Networks(SNNs)are proposed to model the behaviors of information transmission and signal processing inside the neuron.Many SNN applications have been implemented,such as forecasting,image processing,spike-based tactile pattern recognition and artificial vision system.These applications generally require massive neurons to interconnect to form a SNN system.Consequently,it is an important research hotspot to investigate an efficient architecture to realize the SNN system.Based on the existing research results,this paper focuses on the hardware implementation of neuron nodes with low resource consumption,the design of efficient interconnection between nodes,and the design of visualization performance monitoring platform for SNN system.The main works of the thesis include:1.The research background of project is firstly introduced,including the origin of the subject and the main research contents and gives the innovation of this paper.Then,the basic knowledge of biological neural network is described,and the advantage of brain inspiration calculation with artificial neural network as computing system is given by comparing the basic principle of general computer.The development and basic principle of artificial neural network are introduced in detail.And then briefly summarizes the research status of the three aspects of large-scale neural network implementation,neuron interconnection communication mechanism and neural network performance verification test platform construction.Finally,the three unresolved problems are summarized,and the corresponding optimization strategies are given.2.,A low resource and scalable neural hardware structure based on the FPGA device is designed.And the hardware resource occupied by the neuron node which reduced by using the computational component sharing mechanism.In the same neuron,multiple synapses share a synaptic computational component;in the same layer of SNN,multiple neurons share a computational component of neurons.The performance analysis results show that this method reduces the hardware resources occupied by SNN,thus the ability of the hardware device to accommodate neurons is improved.3.Based on the proposed hardware structure of the neuron node,a routing mechanism with simple logic and low resource consumption is proposed.The routing mechanism is used for the interconnection communication mechanism of the neuron hardware node in the hardware implementation of SNN.A broadcast-based Network-on-Chip router is used for the basic working unit of the routing architecture.An efficient routing scheduler is designed to propagate irregular spikes between neurons,effectively.The results of performance evaluation show that the architecture can effectively transmit the spikes between neurons in various spike scenes,and it has lower hardware resource cost.The architecture also maintains the scalability of large-scale SNN hardware system.4.A visualization performance monitoring platform is designed,which is used as functional verification and performance monitoring of SNN hardware structure.The monitoring platform has the advantages of lightweight design,good human-computer interaction interface and versatility,and further improves the efficiency of system function verification and performance evaluation.It provides auxiliary functional verification and performance analysis for the design of SNN hardware system.