Design Of Digital Background Calibration Algorithm For TIADC Based On Fractional Delay Filter

With the rapid development of the integrated-circuit technology,many advanced applications such as optical fiber TV,home cinema,boardband wireless communication and high-performance oscilloscope have been come out.All of these rely on analog-to-digital converters?ADCs?,which link the analog world with the digital world.Newer applications require the speed and performance of ADCs more strictly.Time-Interleaved ADCs?TIADCs?can linearly improve the sampling rate of data accqusition system by increasing the number of channels in terms of maintaining the slice's accuracy.In fact,mismatches between channels including offset mismatch,gain mismatch and sampling clock skew decrease the performance of prototype ADCs sharply.Consequently,Researches on the calibration of TIADCs are always the hotspot in the region of high-performance ADCs.In this thesis,the basic principle of multi-channel TIADCs and their impact on performance of system have been studied.Based on this,this essay proposes an all-digital background joint calibration scheme for the correction of three mismatches in TIADCs.Firstly,a cascaded calibration algorithm based on LMS iterative adaptive is applied for the correction of offset mismatch and gain mismatch errors.Afterwards,according to the characteristic of signals'average energy and auto-correlation,the subtraction of the results of multipliers is proportional to the sampling clock skew.Finally,the extracted estimation of sampling clock skew is used as the input of fractional delay filter to compensate for the skew error.Moreover,this essay proposes two compensation algorithms based on fractional delay filter.One is implemented on interpolation restructure,it is competitive with less hardware to compensate for skew error.The other is implemented on modified Farrow fractional delay filter,its coefficients of weights are available easily and flexible by adjusting the lengths of filters.The experimental results indicate that the algorithm has effectively improved the dynamic performance of TIADC system.The algorithm proposed in this thesis is suitable for inter-channel mismatch calibration of TIADC system with arbitrary number of channels.Firstly,the behavior simulation results of multi-channel TIADC system conducted on Matlab revealed that the SNDR and SFDR increased from 34.0dB and 39.4dB to48.89dB and 68.6dB respectively for input signal frequency at 0.41).Afterwards,the critical data path of calibration algorithm is converted into HDL,and the simulation results conducted on RTL behavior level revealed that the calibration algorithm results in 47.5dB SNDR and 58.7dB.Finally,The matching digital background calibration algorithm is verified by FPGA and implemented by ASIC respectively on Four-Channel 8-bit 1GS/s TIADC system.The verification results of FPGA revealed that the SNDR and SFDR of TIADC system results in 46.4dB and 56.6dB for input signal frequency at 400MHz,which proved that the calibration algorithm is correct and effectively;At the same time,the physical design of ASIC is implemented on TSMC 130nm technology and the digital layout is generated at last.