Design And Implementation Of Data Processing In DC Power Supply Tester

The accuracy and stability of the DC power output characteristics directly affect the reliability of various electronic,communication,and automation equipment.With the rapid development of the power electronics technology,It is particularly important to evaluate output characteristics of aDC power equipment.The DC power supply tester is specially used to acquire the power supply output signal at highspeed acquisition,then process and waveform of the signal data in realtime,which solves the difficulty of using a single testing instrument to test numerous DC power test items.This paper focuses on researching the data processing system of DC power tester project.The goal is to cover the performance requirements of DC power supply output characteristics in terms of accuracy,sampling rate,resolution and bandwidth,as well as waveform capture and analysis functions.This paperresearches the theoretical basis and implementation of data preprocessingmodule and data storage module of the data processing system by adopting the FPGA technology.The main contents are as follows:1.This paper first introduces the overall architecture of the DC power tester.The ARM rich peripheral resources are used to implement the interface protocol conversion between the FPGA and the industrial control motherboard according to the data transmission and isolation requirements between them.Then the ADC + FPGA + ARM + CPU architecture ofthe data processing system is designed.Afterwards,this paper describes the data preprocessing and storage scheme of the system based on FPGA technology,mainly including the scheme of increasing the ENOB(equivalent resolution),the scheme of the digital filter,and the basic structure of the storage module.2.Design a real-time processing scheme for acquired data according to the resolution and bandwidth limitation requirements of the system,which mainly includes two aspects: Based on the principles of oversampling with moving average,the equivalent resolution of theADC quantized data isincreasedto16 bitin the frequency range of DC~5.6MHz;Then design thedigital filter which has adjustable cut-off frequency between 20 Hz and 2MHz under the system clock whose frequency is 200 MHz.This paper usesCIC filtersto implement the downsampling and upsampling of the data.anddesigns a compensation filter to solve the problem of uneven passband caused by high downsampling,simultaneously improve the structure of CIC filter to reduce its operation bit width.3.Implement the storage and transmission of waveform data.This paper first designs a trigger module to improve the convenience in capturing transient signals by responding to external control signals as trigger signals and setting trigger delays.Thenthe trigger and read-write control logic of the normal storage mode and large-capacity storage mode isdesigned.By the waythe storage depth of the large-capacity storage mode can be switched among 10 gears,in which the maximum storage depth of a single channel is 100 MPts.Finally,the data transmission between the FPGA and the subsequent module is inplemented.Through testing and verification,the equivalent resolution of the acquired data reaches 16 bit.The digital filter cut-off frequency can be adjusted in real time within 20 Hz to 2MHz;Waveform data can be displayed stably on the screen.In deep storage mode,the storage depth can be changed as needed.The maximum storage depth is 100 M data points per channel.