Research And Implementation Of Fault Channel Modeling For Power Line Fault Location

As the carrier of power transmission and power line communication,power line has been popularized in every corner of life.In recent years,failures such as short power lines and broken circuits due to aging insulation,external force destruction,and chemical corrosion have been common occurrences,which have seriously affected the reliability of power line transmission.How to accurately locate and eliminate faults has become a hot issue in the field of power line research.At present,the research of power line fault is mainly divided into two parts: power line fault location algorithm and power line fault channel modeling.The traditional power line fault location algorithm has the problem of insufficient fault location accuracy when the reflected signal attenuation is large or the SNR is too low.Moreover,there is a lack of research on the complex topological condition in the power line fault channel modeling.In addition,the research and development of power line fault detection products must be tested in various scenarios,but a large number of tests will cost a lot of manpower and financial resources.Based on this,this thesis proposes a high anti-noise power line fault location algorithm,a complex topological power line fault channel frequency calculation method,and a unified power line fault channel simulation platform.First,this thesis analyzes the research status of power line fault channel modeling and power line fault location technology;combining with the basic knowledge of power line fault basis and power line transmission characteristics,the power line fault location method under Y-branch topology is briefly introduced.Secondly,the backbone path is determined by the length matrix,and then the impedance update of the branch topology is controlled based on the breadth-first search algorithm.At the same time,combining with the modified transmission matrix modeling method,the calculation method of the frequency response of the power line fault channel under the given branch topology is proposed.The feasibility of the method is verified by actual test.Thirdly,the thesis implements the fault channel simulator through field programmable logic gate array(FPGA).The power line fault channel simulator can simulate different types of faults in a given branch topology,which providing a convenient and effective hardware platform support for the testing of power line fault location products.Finally,to improve the accuracy of fault location in low SNR,the principles and shortcomings of existing generalized cross-correlation,adaptive delay estimation,and sparse reconstruction delay estimation algorithms are studied in the thesis.Then sparse reconstruction fault location algorithm based on diagonal slices of mutual third-order cumulative spectrum is proposed because the high-order cumulative spectrum of Gaussian process is zero.The effectiveness and accuracy of proposed algorithm is verified through simulation experiments in Gaussian white noise environment.