Study On Active Power Filter With Fault-tolerant Multilevel Topology

As an important device for improving power quality,multilevel active power filters have accurate current detection capabilities and efficient dynamic compensation performance.Traditional multilevel topologies have complex control in applications,many power devices,and need to increase fault tolerance.Redundancy brings disadvantages such as increased costs.Therefore,this paper proposes a multilevel active power filter with fault tolerance.Compared with traditional power topology,it can reduce the number of power switches and drive circuits,and reduce the total cost of the inverter.The balanced control and modulation strategy of multi-level fault-tolerant topological active power filters under normal and switched fault-tolerant conditions are completed.And grid phase lock and harmonic compensation when the grid is unbalanced.First of all,this paper comprehensively investigates the current research status of multilevel active power filter topology and fault-tolerant topology,and summarizes the structure and current detection methods,modulation strategies,and voltage equalization control of traditional multilevel topologies.An improved multilevel fault-tolerant topology is proposed,the topology working principle of the topology in normal and fault conditions is analyzed,and a mathematical model of the topology is established,which is compared with the traditional multilevel topology.Secondly,a multilevel fault-tolerant topology is applied to the active power filter.The ip-iq harmonic current detection method is used.The current tracking control is selected from quasi-PR control.Software voltage equalization control and hardware voltage equalization.In the unbalanced three-phase power grid,an all-pass filter phase-locked loop is used to phase-lock the unbalanced power grid,and the control strategy for the unbalanced power grid is analyzed.Thirdly,MATLAB / simulink software was used to build a simulation model of the improved multilevel fault-tolerant topology APF system.The simulation resultsverified the APF’s fault tolerance and voltage balance control ability,and the ability of APF’s harmonic current compensation under grid imbalance..Finally,the circuit parameters of the multilevel fault-tolerant APF system are calculated and the main circuit is built.Design the core algorithm board with DSP +FPGA main control chip and three-phase control board with FPGA core and peripheral circuits.Design the DSP main program.The FPGA program includes A /D sampling program,high-speed optical fiber serial communication,carrier layer PWM program,etc..The debugging of the multi-level fault-tolerant APF system is completed.The final experimental results are consistent with the simulation results,which proves the correctness and feasibility of the multi-level fault-tolerant topology APF.