FPGA Design And Implementation Of Frequency Response Masking Digital Channelizer

The digital channelizer for on-board flexible transponders combines the advantages of transparent transponders and processing transponders,reduces the complexity of on-board devices.It can switch non-uniform bandwidth signals,make channel division more flexible and communication capacity larger.It maximizes the utilization of satellite resources,it can also meet the requirements of multiple sampling rate conversion and reduce system workload and storage.The core part of the flexible transponder is the digital channelizer,and the key part of the digital channelizer is the filter bank.The research goal of this thesis is to achieve a low complexity,low splice jitter,and high spectral efficiency filter bank structure.The main work of this thesis is as follows:The existed filter banks,such as DCT-FB,DFT-FB,are studied,and their mathematical principles are derived,the performance,advantages and disadvantages of the implementation are clarified.For structure of the filter bank,the FRM technology that shortens the transition band between the sub bands under the condition of constant complexity is analyzed,a structure with lower complexity is designed in the case of mathematically equivalent,and the data rate of FPGA system is reduced.The transfer function of the filter bank is derived,and the reconstruction error of the filter bank is represented in the form of matrix.The error optimization direction of DFT-FB is given.A nearly perfect reconstruction onboard channelizer of low-complexity combined Frequency Response Masking with Modified Discrete Fourier Transform is proposed.Where the FRM structure can design a low-pass FIR prototype filter with a steep transition band and a low complexity,the MDFT filter bank structure can mostly eliminate the adjacent band aliasing.Replacing the structure of the FRM that is not suitable for the adjacent band splicing by a high-pass and low-pass filter complementary structure,then the splice jitter can be reduced.The upsampling rate in the MDFT structure is adjusted to make it suitable for the odd-even split channelizers.Then based on these two structures,a new structure is put forward,which is more suitable for non-uniform bandwidth applications.Simulations show that this method has lower computational complexity,steeper transition band and narrower guard interval,and smaller reconstruction error.Based on the proposed scheme,a synthesizable VHDL program of whole system was designed,and the structure of the specific IP core used in this design,such as 36 K Block RAM and DSP48 E,was analyzed.Made full use of their characteristics,designed the multiplexing connection mode and control timing,performed modelsim simulation and matlab analysis,and finally completed the FPGA implementation of the entire channelizer,the performance degradation from matlab to FPGA is almost negligible.