Research On Digital Method Of New Generation Motor Drive Chip

With the reduction of energy reserves,energy conservation and emission reduction has become an urgent problem for the whole society.The development of automobile work efficiency has been widely recognized as an important plan to improve energy security and establish an environmentally friendly economy.The core of the car is the vehicle drive motor system,and the motor drive chip is used as the control hub in the system.It integrates digital and analog control IC and DMOS power devices,and can be used to drive inductive loads such as DC motors?stepper motors and relays.How to design a new motor drive IC with higher efficiency and reliability,in line with miniaturization,integration and intelligence has become a important research topic.In recent years,the most obvious improvement in the efficiency of the drive system is the synchronous rectification technology.For this reason,a new generation of motor drive chips,that is,synchronous rectification chips,which are required for the automotive motor system,have appeared.In order to ensure stable and reliable operation of the driver IC in various complicated conditions,especially in automotive electronics applications,reduce the internal power consumption of the driver chip,and increase the regulation of the motor load under different use conditions.So carrying out the digital method research for the new generation motor drive IC of synchronous rectification.For the low power consumption and high precision requirements of automotive motor drive chips,combined with digital logic design,usuing the ultra-low power Trimming calibration module replaces the traditional calibration scheme and designing the high-precision voltage and current system.It is applied to the vehicle synchronous rectification driver IC.For the basic principle and special load requirements of the vehicle synchronous rectification driver IC,the frequency detection and calibration digital control module?FM module?for regulating the MOT time and the chip operation mode is designed.Based on a 0.35?m BCD process platform of a foundry,using Cadence related tools to complete the full process angle of high-precision voltage and current systems,Monte Carlo simulation.Using Modelsim,VCS and other tools to complete the verification and synthesis of the FM module code,and the FM module of the parasitic parameters is post-imitation verified after extracting the post-imitation.Taping out the IC after drawing the layout,and the result of the IC is tested.In the sample of the measured stream,the maximum error of the digital optimization target V_BGINT voltage is-0.009V⁰.002V,the maximum error of I_REFOricurrent is 0.19?A,and the maximum error of AVDD is 0.026V.At the same time,the calculation and control of the MOT time and the chip working mode are realized within the error tolerance range,and the expected goal of reducing the internal power consumption of the chip,increasing the adaptability of the chip to the load and improving the working efficiency is achieved.