Design And Implementation Of DSP Subsystem In Improved Data Link Terminal

As a data information system dedicated to the battlefield communication environment,the tactical data link can effectively improve the decision-making efficiency,command speed and coordinated combat capability of the military,and therefore largely determines the strength of the military's information warfare.As the operational requirements continue to change and become more complex,the original data link needs to advance with the times in terms of concepts and functions.Therefore,the evolution of the old data link has always been a hot trend in the development of data links.The improved data link terminal in which the thesis participates,is designed to improve the original data link with increasing the data speed and realizing the networking function,so as to meet the test and verification requirements of multiple data link integration and network convergence related technologies in the project.The main content of the thesis also centers on the design and implementation of the DSP subsystem in the improved data link terminal.Firstly,the thesis reviews the background and current development directions of the tactical data link to emphasize the significance of the research direction,and outlines the overall structure of the thesis.Subsequently,the thesis completes the overview of the hardware platform and the partial parameters' design of the improved data link system,and divides the signal processing in the DSP subsystem into two parts:coding transmission and decoding reception,to realize the corresponding functional module construction respectively.In order to overcome the problems of channel decoding and reception,the thesis designs and implements the improved frame synchronization algorithm,the frequency offset correction algorithm and the phase offset correction algorithm.In the simulation and actual test,at the cost of reducing the synchronization peak,the improved frame synchronization algorithm increases the tolerance of system's frequency offset by more than 10 times comparing with the original frame synchronization algorithm,and the frequency offset and phase offset correction algorithm owned the advantage of simple implementation while ensuring the accuracy of correction.Based on the construction of the link function module,the thesis realizes the interactive logic design between the PC subsystem,DSP subsystem and FPGA subsystem,and implements the time-slot-allocation networking function in data link.The overall operation process of the DSP subsystem is analiyzed from the perspective of program operation,and the design and implementation of the DSP subsystem are summarized.Finally,the thesis verifies the function of each functional module in the DSP subsystem and the integrated improved data link,summarizes the results and shortcomings,and discusses the subsequent improvements and the development directions of related technologies.