Design Of Three Phase Intermediate Frequency Voltage Adjustable Precision Signal Source

At present,in the field of aerospace aircraft for signal source test not only in the presence of poor reliability,low accuracy,large size,high cost,high risk of operation;and to test the software is proprietary,bring great limitation for accurate testing and automated testing of aircraft.In order to meet the precision automation requirements of the space shuttle test,this paper aims to design a program controlled three-phase sine precision signal source using DDS technology.This paper first introduces the design theory of three-phase sine signal source,working principle characteristics,including three-phase sinusoidal AC sampling theorem and DDS technology,which focuses on the working principle of DDS is proved and its 4 main parts:low-pass filter,ROM waveform table,phase accumulator,DAC in detail description.And through the DDS output waveform of the ideal and non ideal condition of spectrum analysis draws two important conclusions,the first is the cutoff frequency of the lowpass filter;the second is to get the key factors of spurious suppression,and on the basis of the proposed 4 methods of suppressing spurious: improve the structure,improve the quality of the phase accumulator,clock waveform ROM table compression,jitter,and theoretical analysis of this technique results in several spurious software simulation results confirm this method,several spurious suppression has good effect.The control part realizes the control of DDS signal generator by single chip microcomputer,calculates the corresponding frequency control words,phase control words or amplitude control words by input information,and controls the output of FPGA through the RS232 interface,and displays the waveform information on the LCD screen.The final design is realized by FPGA chip output waveform data transmitted to the high speed DA chip through 9 order elliptic filter output analog waveform signal;and the output waveform can control the frequency,amplitude and phase of the chip size,the frequency range from 300 Hz to 500 Hz,step 0.01Hz;range from 0~6V,step 0.1V phase,adjustable range: 0~360 degrees,0.1 degrees,the final adjustment precision: LCD1602 display by LCD parameters.The model of the FPGA chip used in this design is that the model of the EP1C3T144C8 N high speed DA chip is ADV7123.