Design And Implementation Of STAP Processor For Airborne Radar Target Detection

As informationization and intelligence developed rapidly,airborne radar expands gradually from military to civilian applications and moving target detection plays an important role in the airborne radar field.As one of the effective technical ways to improve airborne radar performance of moving target detection,although it appeared over 40 years,the interest in space-time adaptive processing?STAP?is still rising all over the world.Taking clutter suppression performance and restriction factors in practical engineering applications into account,the performance of reduced STAP algorithm as well as several key technologies such as real-time implementation are researched in this dissertation and this study is supported by national ministry projects.The main contents are listed as follows:1.A three Doppler channels joint iterative adaptive processing?3CIAP?based on adaptive structure reduced dimension method and fixed structure reduced dimension method is propoed.The optimum STAP algorithm has the best performance in suppressing clutter,but the complexity of large signal vector space is too high to applied to the actual project directly.Besides,the existing reduced dimension methods have poor real-time performance and they are not easily applied to engineering.Based on advantages of the above two reduced dimension structures,a two-stage cascading reduced dimension method among which the first stage is used to reduce temporal domain degrees of freedom?DOFs?by doppler three-channel joint adaptive processing?3DT?algorithm and the second stage is used to solve weight vector by correlation subtraction algorithm multistage wiener filter?CSA-MWF?is put forward in this dissertation.Theoretic analysis and experiment shows that comparing with 3DT and optimum STAP methods,the clutter suppression performance losses of proposed method is less than 3dB,while the calculation cost is reduced by nearly two orders of magnitude and more than 1/2 orders of magnitude respectively.2.The pipelined architecture is used to complete the space-time subspace transformation and CSA-MWF circuits.They are two key technologies of 3CIAP which is proposed in this dissertation.At bottom,the former is the same as fast fourier transform?FFT?.By analyzing and comparing existing FFT processor architectures,considering power,speed and area,the pipelined FFT processor is adopted to complete 128 points transformation.The latter can be mapped into forward recursion,backward recursion and weight vector solution three modules.Forward recursion module is used to accomplish orthogonal decomposition of transformed domain data.Backward recursion module is applied to filtering expected signals.And the weight vector solution module is designed to make scalar weights convert into the optimal weight vector.In order to improve throughput,all three modules are designed to be pipelined architecture.3.A parallel processing system based on multi-chip field programmable gate array?FPGA?is designed and verified.Owing to limited resources of one FPGA and high requirement of real time,the parallelism of the proposed algorithm is analyzed in this dissertation.Then the algorithm is divided into several child processes.Considered the proposed algorithm,global flow scheme is applied into the whole design to increase resource utilization and local parallelism is adopted into child process to hike up throughput.A verification platform is built with Matlab and Modelsim.Modelsim and Matlab simulate the test data produced by Matlab respectively,then these two simulation results are compared.The results verify validity of designs and the final relative error is at 10^-3 level which is meet accuracy of radar signal processing.