| According to the development of modern memory industry,the working voltage of DDR memory is becoming lower and lower,but the data rate is increasing with the progress of science and technology.In order to meet the power requirements of DRAM such as DDR1,DDR2 and DDR3,and pursue the goal of miniaturization and integration,so the DDR memory needs a more efficient and stable power management system.In all power management chips,Buck DC/DC converter is a good choice for DDR power supply because of many advantages,such as wide input voltage range,low power consumption and high efficiency,etc.Firstly,this thesis introduces the fundamental principles and control modes of Buck DC/DC converter in detail,and models the converter's power stage with small signal in CCM,DCM and BCM,compares the advantages and disadvantages of different feedback control modes and sampling modes.Then,a current mode adaptive on-time(CMAOT)control strategy is proposed,and this control mode adds a current control loop to the conventional constant on-time(COT)control mode topology,so that the system has fast transient response performance and does not need slope compensation.At the same time,the working frequency of the system is a constant value in steady state,which decrease the processing difficulty to EMI,because on-time is set to be self-adaptive adjusted with the cooperation of a pseudo-constant frequency control technology.Last but not least,a technology called internal pseudo-PLL is presented to improve the working frequency characteristic by adjusting the on-time of the converter according to the departure of working frequency and referenced frequency,and then achieve the goal of tracking and locking the working frequency and the reference frequency.In addition,as for the external synchronous PLL,It not only realizes the function of external synchronous frequency,but also forms a double PLL system with the internal pseudo PLL to coordinate and control the internal and external working frequency characteristics of the system.Based on the above analysis,a triple-terminal output Buck DC/DC Converter XD1890 with high-efficiency for DDR memory application is designed,and the whole structure is formed,the functional modules are divided.This chip can output stable triple-terminal voltage: supply voltage VDDQ,bus terminal voltage VTT and reference voltage VTTR.And it also integrates many protection circuits besides the soft start function,such as over-temperature protection,over-voltage and under-voltage protection and current limiting protection,etc.Meanwhile,the DCM mode will be launched automatically in light load application to improve the conversion efficiency.Moreover,the theoretical basis for the selection of chip peripheral devices and frequency compensation network for the stability of feedback loop have been provided.With regard to the prediction of power consumption and efficiency of the system,some design considerations and reference opinions are also given in this thesis.Base on the realization principle of the main sub-module circuit of this chip,the reference voltage circuit,the adaptive on-time(AOT)generator and the high voltage driver circuit are designed.The circuit simulation of chip was established by the cadence software platform and 0.35?m BCD process.The simulation results show that XD1890's minimum output voltage is only 0.6V,full load current of 4A,the conversion efficiency is up to 92%.When the load current is changed at full range,the output voltage return to stable for about 40?s,and the switching frequency has changed,the external phase locked loop make system frequency resume normal characteristic for about 44?s.So the proposed system achieve the expected design objective,such as large load current,high efficiency,fast transient response,stable working frequency. |
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