Research And Design Of High Precision 24-bits Sigma-Delta Modulator Based On MEMS Geophone

With the continuous development of seismic exploration,there are fewer and fewer resources in shallow layers.People begin to explore and develop deep geological resources,which requires higher and higher resolution of seismic acquisition data.Seismic exploration instruments,as the key equipment for data acquisition,directly affect the quality of seismic data,and traditional analog geophones are not enough to meet the requirements.In recent years,due to the tremendous development of microelectronic technology,the sixth-generation all-digital geophone based on MEMS(Micro-Electric Mechanical System)technology has become a development trend.In contrast,the response characteristics of MEMS geophones to seismic signals,such as large dynamic range,low distortion,low noise,and frequency bandwidth are its main advantages.Sigma-Delta(Σ-Δ)analog-to-digital converter(Analog-Digital-Converter,ADC)has the characteristics of achieving high resolution and is widely used in MEMS geophones.TheΣ-ΔADC is composed of the modulator of the analog module and the filter of the digital module,and its resolution is determined by the modulator.Therefore,the key to measuring the performance of theΣ-ΔADC is the modulator performance.The core technology of the modulator is oversampling and noise shaping.This thesis focuses on the research and design of the modulator module inΣ-ΔADC applied to MEMS geophones.By studying the different structures of theΣ-Δmodulator,considering the stability and the suppression of noise,this paper uses a1-bit fourth-orderΣ-Δmodulator system structure with a chopper,using a feedforward path hybrid channel technology used in conjunction with the feedback channel.Through research on system-level design and selection of appropriate feedforward and feedback coefficients,in-band quantization noise can be effectively suppressed.Due to the non-ideal factors in the circuit,the theoretical signal-to-noise ratio will deviate from the design of the circuit system.From the perspective of circuit design,the improvement of the circuit is used to suppress the interference of non-ideal factors on the performance of the modulator.The main innovation of the circuit design is the improvement of the first-stage integrator.One is the use of chopper technology to eliminate the low-frequency 1/f noise of the integrator;the second is the use of a class AB operational transconductance amplifier with class AB input stage,nonlinear current recovery structure,gain bootstrap structure,greatly increased the speed and accuracy of the first stage integrator.Under the Cadence EDA tool,this paper designs,simulates and optimizes each sub-circuit and layout of the modulator based on the SMIC018 process.After DRC,LVS,ERC inspection and post-simulation verification,the chip is finally taped out.The sigma-delta modulator designed in this paper has a signal bandwidth of 2KHz,a sampling clock of 512KHz,an oversampling rate of 128,the power consumption is less than 5m W,and the effective chip area of 1.765×1.752mm~2.The simulated signal-to-noise ratio of the modulator is 101d B and the effective number of bits is 16.4bits;the test signal-to-noise ratio of the modulator chip is 66.25d B and the effective number of bits is 10.7bits.