Design Of Low Power Matched Filter In GPS Acquisition Engine Using Approximate Computing

The matched filter is the key component in the Global Positioning System receiver.With the development of the Internet of things,the power consumption of the system can pose a great challenge to the battery life of mobile devices.Matched filter includes correlation array and storage array,where addition circuit to realize correlation is an important source of the power consumption,so the focus of this thesis is to research addition circuit and implement low power matched filter.Considering that the matched filter is a linear filter which provides the maximum signal-to-noise ratio(SNR),the accuracy can be in exchange for reduced power consumption by using approximate computing.Firstly,a multi-bit digitally-controlled delay element addition circuit is designed.An addend acts as the control signal of delay element and is converted into a monotonous delay consistent with the value of itself.The accumulated delay is finally converted into digital by quantization circuit.Due to the existence of static current,its power consumption is higher than that of digital addition circuit.Secondly,a single-bit digitally-controlled delay element addition circuit is designed.Bits with the same weight are control signals of a delay chain and different weights are for different delay chain.High frequency periodic signal generated by the oscillator composed of delay elemenrts acts as the clock signal of counters which convert cumulative delay to digital.Quantitative outputs of different delay chains are weightedly summed in the digital domain.Without considering the power consumption of the quantization circuit,its power consumption is only 10%of the digital addition circuit.The single-bit digitally-controlled delay element addition circuit and dynamic register are used to form correlation array and storage array seperately.Two-point method is ultilized to calibrate quantization error and the SNR loss is controlled within 2dB compared with precise matched filter,lower than approximately 3dB SNR loss of matched filter using switched current source array.Physical design of the matched filter whose length is 1024 with 4-bit input data is finished using SMIC 28nm process technology.Post simulation shows that its power consumption is 130.1?W at 0.55V voltage with 60ns cycle.Comparative analysis of normalized energy efficiency and area efficiency of the matched filter in this thsis and other papers shows that energy efficiency and area efficiency of the proposed matched filter in this thesis are 131.5TOPS/W and 0.713TOPS/mm~2.The matched filter using switched capacitor array with 331.3TOPS/W energy efficiency is applicable to circuits that do not require high area efficiency.The energy efficiency of the digital matched filter,the matched filter using approximate adder and the matched filter using switched current source array are 28.7TOPS/W,71.2TOPS/W,and 97.2TOPS/W respectively,which are all lower than that of the proposed approximate matched filter.In conclusion,the proposed approximate matched filter has certain advantages in terms of both energy efficiency and area efficiency.