The Design Of H.264 Video Compression And Encoding Based On SoC-FPGA

H.264/AVC,the classic video codec standard,has a vital position in the field of video image compression and transmission.However,it is difficult to meet the requirements of real-time codec using software solution due to the high computational complexity of H.264 coding algorithm.Therefore,it is necessary to use FPGA devices to accelerate.As one of the key technologies of the H.264 standard,inter-frame prediction has a large amount of calculation.Take this into account,the So C-FPGA is used in this paper to do the co-design of hardware and software,and the hard core of ARM is used to run the linux system to realize the collection,schedule and overall control of the video stream.The hardware circuit is used to accelerate the algorithm and improve the real-time performance of the system.In this paper,the working principle of each key technology in H.264 standard is introduced and analyzed.The whole pixel motion estimation technique and the sub pixel motion estimation technique are emphatically analyzed,and the circuit implementation is carried out using the So C-FPGA platform.In view of the characteristics of the modules above,8×8 size sub block is used as the minimum unit of tree like segmentation to reduce the amount of computation and reduce the consumption of hardware resources.At the same time,an improved hardware circuit for parallel data processing is proposed,which improves the data throughput.The 4×4 size block circuit is used to carry out the operation,combining the data processing characteristics of pixel interpolation to merge the vertical pixel data.Therefore,compared with the traditional structure,the hardware resource consumption and data processing cycle are reduced,and the coding efficiency is improved.The design of H.264 video compression and encoding system is achieved on Altera So C-FPGA Cyclone V 5CSEMA5F31C6 N device.The RTL code is implemented for these modules,while the circuit is simulated by Modelsim.Quartus II is used to perform timing constraints,circuit synthesis,and post-imitation in this circuit,which ensures the correctness.The tailored Linux system is operated in the ARM core.V4L2 API is utilized to realize the real-time video data capture of camera in the embedded system.The data collected is transmitted to the FPGA hardware circuits by AXI bus to perform acceleration operation of inter-frame prediction.Moreover,the returned data of the hardware circuit is processed,and the compressed data is stored using ARM core.In real time data processing for 640 x 480P@30FPS video signals,it consumes 26979 ALMs,29710 registers,52 M10 KRAMs and 31 DSPs,which meets the expected requirements of the project.