A Design Of High-speed Data Reconciliation System Based On FPGA Heterogeneous Computing

Quantum key distribution(QKD)is the most critical part of quantum secret communication systems.And the data reconciliation is an integral part of the QKD system.It is used to remove and correct the error code words caused by the channel's thermal noise and the presence of eavesdroppers.How to improve the speed of CV-QKD data reconciliation has always been a problem that needs to be solved in the industry.The emergence of OpenCL(Open Computing Language)provides a new solution to this problem.OpenCL can process data at high speed through parallel computing.And the emergence of AOCL(Altera SDK for OpenCL)enables FPGA parallel architecture to perform OpenCL parallel programming.FPGA can achieve high performance with ultra-low power consumption.In combination with its highly parallel nature,it has been became a trend that we choose the heterogeneous parallel programming architecture combined OpenCL and FPGA to accelerate computing.This article does the following work on how to improve the speed of CV-QKD data reconciliation:I improved the static cross-reversible circular linked list data structure of the laboratory's original storage LDPC code sparse parity check matrix H making the data structure conforming to the OpenCL programming specification;and the parallel kernel design and optimization of the Slepain-Wolf algorithm are realized.Using DE5-Net development board as FPGA heterogeneous platform,OpenCL architecture and C/C++as language tools,I implemented FPGA-based CV-QKD data reconciliation heterogeneous acceleration scheme,and compared the speed of accelerated data reconciliation with the original serial algorithm at CPU platform,and analyzed and compared the acceleration effect and the performance.From the experimental comparison results,it can be seen that the scheme's decoding speed can reach 42.41kbit/s that CV-QKD data reconciliation parallel acceleration algorithm scheme on FPGA-based heterogeneous computing,the channel SNR is 4.9dB,2×10~5 continuous variable sequences are reliably coordinated,and the number of iterations is 100,and on the premise that the coordination efficiency is 91.97%.Compared with the serial algorithm of the CPU platform,the calculation speed is increased by nearly 6 times.