VLSI Design Of TCP/IP Protocols For Quantum Key Distribution System

Quantum secure communication has unparalleled technical advantages and is a cross-disciplinary research field of quantum physics,electronic information science and computer science.The quantum key distribution(QKD)system is an important part of the quantum secure communication.In addition to the basic quantum channel,the QKD system also needs classical communication networks for basis comparison,identity au-thentication,error correction and privacy amplification.The classic channel processing of QKD system is completed by TCP/IP protocols,which is the set of basic network protocols.At present,the QKD system is made up of many chips and devices,and there are various defects.With the development and maturity of QKD technology,the system is developing towards miniaturization and integration.The design of QKD SoC is of great significance to improve the security of quantum key.The TCP/IP hardware structure designed in this thesis is an important part of the central control and data processor for quantum communication system,which mainly completes the encapsulation,unsealing and management of the TCP/IP messages.First,by interpreting the TCP/IP protocols and analyzing the related principles,functions,message formats,the overall design of the system framework is completed.Then,by utilizing the top-down design method,the system is divided into modules.Then the internal structure,the external interface signal and the interconnect scheme of the mod-ules are designed.The timer circuit,the serial number generation circuit,the checksum calculation circuit and the state machine of each module are introduced,and the simpli-fied structure of TCP,UDP,IP,ICMP and ARP is realized.The modules are designed with Verilog language in detail.Then,the verification platform is built,and the network tranmission function is verified through RTL simulation and FPGA.The results show that the proposed design can meet the network bandwidth requirement of QKD.Finally,the synthesis and layout are carried out using Design Compiler and IC Compiler based on the SMIC 55nm standard logic cell library,and the parameters of timing,area and power are obtained.The main contributions of this thesis are as follows:First,the TCP/IP hardware structure can handle the network data independently,and the CPU does not need to parse the protocols,and the risk of leaking the key caused by the software defects is re-duced.Second,the implementation of the protocols of TCP,UDP,IP,ICMP and ARP can meet the requirements of network transmission.Third,according to the character-istics of TCP protocol for byte stream processing,the mapping relationship between the sequence number,acknowledge number and storage address of TCP is realized,and the complexity of the system for data processing is reduced.Fourth,by adopting out-of-order segment reorganization method,maintaining the complex link list in the hardware is no more needed,instead,the disorder data is directly placed in the appropriate address in the memory.Fifth,the retransmission of the segment is realized,and only the specific information of the segment is saved which results in the reduction of circuit size.