Based On The Integration Of SOI Silicon Magnetic-sensitive Triode Differential Structure

In this paper, the integrated SOI silicon magnetic sensitivity transistor with differential structure is given based on the analysis of the basic structure, working principle and characteristics of silicon magnetic sensitivity transistor with plan structure, and the integrated structure is comprised of two SOI silicon magnetic sensitivity transistors(PSMST1, PSMST2) with opposite magnetic sensitivity directions and collector load resistors(RL1, RL2), that owns a common emitter(E), two bases(B1, B2), two collectors(C1, C2), and two collector load resistors. The simulation models of plan silicon magnetic sensitivity transistor were established by ATLAS software based on the basic structure. The effects of base length(L), base length width(w), emitter width(WE) and substrate type on it IC-VCE, magnetic and temperature characteristics have also been studied to realize structural dimensions optimization. On this basis, establish the simulation model of the SOI silicon magnetic sensitivity transistor with differential structure for simulation analysis.Base on above, an integrated SOI silicon magnetic sensitivity transistor with differential structure is studied, designed, and produced on a p-type high-resistance(?>1000 ?·cm) SOI substrate whose crystal orientation is <100> at the device level. The proposed SOI silicon magnetic sensitivity transistor with differential structure are produced with different geometry dimensions. Several testing devices, including a semiconductor parameter tester(Keithley 4200), a magnetic field generator system(CH-100), a multimeter(Agilent 34401A), a constant current source(Rigol SD120), a constant voltage source(Rigol DP832) and a high/low temperature chamber(Obis GDJS-100LG-G) are used to test the IC-VCE, magnetic and temperature characteristics of the proposed transistors. Based on the testing results, the best geometry dimension combination of the transistors, that is WE=400 ?m, w=50 ?m and L=100 ?m is selected. With the dimensions, when VDD=3.5 V and IB=0.5 m A, the absolute magnetic sensitivities of the collector voltage output of the SOI silicon magnetic sensitivity transistor and the SOI silicon magnetic sensitivity transistor with differential structure are 68.97 m V/T and 132.72 m V/T, respectively. The relative temperature coefficients of their collector voltage output are 548 ppm/? and 376 ppm/?, respectively. The experimental results show that the integrated chip of SOI silicon magnetic sensitivity transistor with differential structure can improve the magnetic sensitivity and temperature characteristics.