Research And Design Of A Multi-Channel Parallel Output Buck DC-DC Controller

The power management chip is the basis for supporting the normal operation of current portable electronic products and precision industrial equipment.The features of high input-low output,excellent efficiency,and fast response make The BUCK switching converter which adopts current-controlled mode meet many current application scenarios.However,under the current trend of low voltage and large load currents,traditional single-chip work will lead to problems such as excessive chip area,severe heat generation,difficult packaging,and excessive device stress.The market demand has led to the emergence of multiple parallel output technologies.This technology has the advantages of reducing device stress,excellent ability to drive large current loads,convenient scalability,and so on,so it has gradually become a research hotspot.The paper first analyzes the current status of the development of switching power supply chips,which is an important part of the integrated circuit field at home and abroad,and consolidates the development trend of the market.In order to solve the current contradiction between low voltage and large current load,a multi-channel parallel chip was designed.The paper firstly analyzes the working principle,modulation method and control mode of the BUCK controller.Under careful comparison,the current mode with good voltage linearity and loop response is selected.Then,the core technologies of multi-channel parallel are studied carefully,including multi-phase interleaving parallel technology,load current sharing technology and capture phaselocked loop technology for parallel chip tracking external multiphase signals.The multiphase interleaving and paralleling technology can significantly reduce the output current ripple.After a full comparison of the mainstream load sharing techniques,this article uses the master-slave load sharing.At the same time,the second-order system response in the control theory is used to analyze the dynamic characteristics of the second-order and third-order charge pump phase-locked loops.The method is designed and used due to its wide range of phase locking and zero phase difference.Afterwards,the previous theoretical studies is adopted to conduct specific chip module design,including the current source providing a reference current source for the entire chip,and a CPPLL that can not only phase lock under multi-channel parallel condition,but also is frequency adjustable when single-chip working.After the module design was completed,the single-chip work with output voltage of 1.8V and output current of 7A was verified firstly in simulation,which based on the 0.35-micron BCD process library.The results showed that all indicators,such as current ripple and load regulation met the expectations.Then an example of two channel parallel system architecture that output 14 A current is built.The simulation results are compared with the typical application of a single chip working and found that the designed chip of the two-channel interleaved parallel doubles the frequency of the output capacitor,significantly reduces the current and voltage ripple,greatly reduces the stress on the energy storage components.All the results met the original design goals.