Research On Analysis Method Of Hierarchical FPGA Hardware Vulnerability

Programmable FPGAs which have the advantages of high speed and high reliability are widely used in wireless communications,consumer electronics,and high performance computing.Recently,with the rapid emergence and development of some technologies,such as 5G,artificial intelligence,Internet of things,and big data,requirements of highthroughput,data parallel computing and other performance are increasing,which will make the application fields of FPGAs more widespread.Therefore,lots of attention should paid to the hardware security of FPGAs,especially security of the design source code.In digital circuits,finite state machines(FSMs)are often used as controllers,which can have a huge impact on the behavior and performance of the circuit.For the hardware security of FPGAs,Verilog source code is taken as the research object in this thesis,the FSM extraction problem is analysed and studied,and the FPGA hardware vulnerability is evaluated based on FSM's transfer condition ambiguity and deadlock states.The main research work of this thesis is divided into the following three parts:1)A method of extracting pseudo-state machines based on Verilog code is proposed.Aiming at the problem of semantic understanding of Verilog source code,this paper proposes an algorithm for extracting pseudo-state machine and designs a simplified compiler.First,by lexical analysis,the character stream in the source code is converted into a lexical unit sequence.Second,lexical units are organized in an abstract syntax tree through syntax analysis.Then,by traversing the grammar abstract tree,each node is visited and its semantics are analyzed,and the states and transition conditions are extracted.Finally,experiments have shown that for any Verilog source program,its pseudo-state machine can be extracted.2)An algorithm of extracting FSM based on a pseudo-state machine is proposed.Aiming at the accessibility of transition conditions in the pseudo-state machine,a strategy to judge the truth or fault of transition conditions is proposed.The unreachable condition in the pseudo-state machine is removed and the complete FSM is extracted.Firstly,the backtracking process of transition conditions is studied in the way of reverse analysis,and the backtracking process is represented by over-dimensional trees.Then,the breadth-first algorithm is used to search for an over-dimensional tree to determine whether the transition condition is true or false.Finally,experiments show that the algorithm can effectively remove the unreachable transition conditions and identify the FSMs.3)An evaluation algorithm of FPGA hardware vulnerability based on FSMs is proposed.For the hardware security of FPGAs,a complete FPGA hardware vulnerability assessment system based on FSMs is constructed.First of all,this thesis focuses on the vulnerability that may be exploited by the attacker in the FSMs,such as ambiguity and deadlock states.Second,the analysis methods of ambiguity and deadlock state are studied,and an algorithm for analyzing FSM vulnerability is proposed.Then,the assessment criteria for the transfer condition ambiguity and deadlock states are defined to evaluate the hardware vulnerability of the FPGA.Finally,experiments have shown that FPGA hardware vulnerability can be evaluated based on existing FSM vulnerabilities in the Verilog source code.