Research On Single-Event Transient Radiation Hardened Technology Based On 65nm Bulk Silicon CMOS Process

Integrated circuits are the heart of every aerospace device.Its accuracy and performance directly determine the safety and suitability of aerospace components.As the size of integrated circuits(ICs)shrinks,and requirements for spacecraft performance and operating time become more stringent in the future,the hardening ability of the circuit chip will be one of the key factors.As circuit integration increases,Single-Event Transient(SET)becomes increasingly important.The voltage and current perturbations caused by the SET may also cause lots of single-Event Effects.According to the survey,we can see that the continuous development of ICs technology,the scale of the circuit is expanding day by day and the soft errors caused by the SET are occurring frequently.Now,it has become the main radiation effect causing the circuit failure.This paper studies and analyzes the soft errors caused by SET,based on the 65nm bulk silicon CMOS process.Meanwhile,This paper proposes an effective SET hardening method.The simulation results show that the proposed new hardening method in this paper can significantly reduce the SET pulse amplitude,thereby the soft error rate induced by the SET is greatly reduced.The results of study provides theoretical guidance for the anti-radiation design of ICs.The core of this paper is as follows:(1)This paper has a deep analysis of the SET generating mechanism and propagation property,and summarizes many general SET simulation methods,based on domestic and foreign research conclusions about anti-radiation design.(2)In order to accurately evaluate Single-Event Transient,the device interior studies must be conducted.Therefore,it is necessary to construct the physical model of the device.The physical model has many advantages.The most important advantage of those advantages is the depth of physical similarity.It can ensure the constructed model more accurate.In this paper,Technology Computer Aided Design(TCAD)tool is used to build the single transistor model,and then it were calibrated to 65nm process HSPICE model from the SMIC company.The required three-dimensional device model has been built successfully after calibration,Next,TCAD will be used to simulate device modeling.The whole process is called heavy ion strike.The next step is that we set different Linear Energy Transfer(LET)values and different supply voltages in order to observe the transient current changes of the single transistor under different conditions.(3)The existing SET hardening method is mainly to adjust the size of the recovery transistor.Based on this,a new hardening structure is proposed.The structure consists of four transistors.NMOS is used in the structure mainly can pull down the voltage of the hit node to improve the SET pulse waveform.In order to take the low power and the variability of the actual radiation environment into account,this paper simulates separately under different incidence LET,incidence angles and supply voltages,based on area-matched(the circuit area remains the same)and drive-matched(the circuit driving remains the same)conditions.Compares with previous hardening methods,the simulation results show that new hardening structure improves the SET pulse significantly,and achieve the expected hardening goal.