Research And Implementation Of Digital Receiver For Duffing Oscillators Array Based On FPGA

At present,the conventional communication technology of non-chaotic signal transmission has been widely used,such as GSM,CDMA and OFDM.The chaotic communication technology of chaotic signal transmission has been studied extensively and deeply,but it has not been applied widely,such as CSK,chaotic CDMA and so on.On the basis of the current researches,this paper presents a kind of digital receiver solution by the chaotic duffing oscillator.The method can detect the conventional 2DPSK modulation signal.The chaotic algorithm is implemented in the FPGA platform.The simulation results suggest that the detection theory of chaotic doffing oscillator for the conventional DPSK signal is more efficient than the conventional demodulational method.The receiver system mainly consists of five parts: analog signal receiving module,AD-free conversion module,duffing oscillator module,zone partition and DPSK demodulation module,and baseband symbol recovery module.The function of the analog signal receiving module is that the spatial signal received by the antenna is amplified and filtered.In addition,it gets the IF signal for the subsequent sampling processing.According to the unique characteristics of chaotic algorithm,this paper adopts the scheme of the analog-to-digital conversion without AD structure.The high-speed voltage comparator takes the place of ADC to convert the IF analog signal into binary digital signal.Altera FPGA development board is adopted as the platform.The detection equation of duffing oscillator is realized in Verilog HDL by parallel and pipeline design.The main function of the algorithm is to detect whether the input signal exists or not.Besides,the idea of the zone partition is a good solution to the problem of intelligent detection.Because it is efficient and accurate for the detection of the signal information by the appropriate parameter settings.On the other hand,the zone partition together with DPSK demodulator for DPSK modulation signal simplifies the structure,and saves hardware resources in the FPGA.The last part is the baseband symbol recovery module,which mainly includes the bit synchronization module,the sampling and decision module.The structure is simple and the algorithm is efficient.In order to debug Duffing oscillators' array digital receiver,this article utilizes the DDS chip AD9854 to generate conventional 2DPSK modulation signal.The signal is transmitted in the form of the I/Q modulation in the Agilent signal generator.The chaotic Duffing oscillator digital receiver can receive and demodulate the 2DPSK signal correctly with the good BER performance.The test results show that the receiver has reached the aim of design.