Design And Implementation Of Blind Estimation Algorithms For Pn Sequence In DSSS Signals

Direct sequence spread spectrum(DSSS)communication technology is a significant method on spreading spectrum.In this decade,the DSSS communication technology has been applied diffusely in mobile communications,tactical communications,and remote telemetry.Based on its advantages such as: anti-interference ability,confidentiality,and easy to implement multiple access communication,DSSS communication technology has been attached more and more importance and the spreading code detection technology has also become a significant study issue.However,the blind estimation of DSSS communication system on a small amount of priori conditions has been an urgent problem of non-cooperative communication needs to be solved and the research on the blind estimation of spreading sequences at low SNR condition is very significance.The detection and parameters estimation for DSSS signals was considered in this paper,the center issue is the blind estimation of PN sequence.First,introduced the basic compositions of DSSS communication system briefly and established mathematical model of DS/MSK signals.On this basis,the detection and parameters estimation for DS/MSK signals based on time-variant finite-average cyclic autocorrelation(referred as CA)algorithm was considered.The parameters included carrier frequency and the code rate.Secondly,blind estimation algorithms of PN sequence based on signal matrix decomposition(SMD)was researched.Introduced the blind estimation algorithms of PN sequence based on eigen value decomposition(EVD)and singular value decomposition(SVD)respectively.Analyzed the EVD algorithm by the eigen value decomposition of DSSS signals and the principle of EVD algorithm in detail.SVD algorithm solved the problem of phase ambiguity in the case of asynchronous signals,using new segmented way to compose a new signal matrix.The blind estimation algorithms of PN sequence based on projection approximation subspace tracking density(PASTd)was researched.Improved the PASTd algorithm by combined the advantages of SVD algorithm.Compared the EVD algorithm?SVD algorithm and the PASTd algorithm in sequence correlation ? convergence rate and algorithm stability.Finaly,the Verilog HDL language realization of PASTd algorithm was researched,with the XC5VSX95 T FPGA chip of Xilinx company's Virtex-5 series as the core processor and ISE14.3 as the software environment.The design of software program was realized by data processing of PASTd algorithm and serial port.Completed simulation work of every modules by Modelsim10.1.Finally,completed the demonstration by experimental verification platform and PC.