Reconfigurable Array Structure And System Scheduling For Energy-efficient Neural Networks For Media Applications

In recent years,with the development of Internet and electronic technology,Artificial Neural Network(ANN)has become one of the research focuses in the field of media applications.Through different weight coefficients,ANN algorithms can achieve different functions.Coarse-Grained Reconfigurable Architecture(CGRA)can be configured to realize different algorithms.With the combination of ANN and CGRA,this thesis focuses on the reconfigurable ANN accelerator for media processing.In this thesis,the Multi-Layer Perceptron(MLP)network is selected to deal with the kernel algorithms in JPEG and H.264.Then,based on the classical reconfigurable neural network system,a reconfigurable neural network system for media processing is proposed,and the key parts of system optimization is reconfigurable neural network array and system scheduling.Then,the characteristics of weight,configuration and data are analyzed.In the aspect of reconfigurable neural network array,the thesis analyzes the data flow of MLP network,and designes a dynamically adaptive routing structure based on computational load,which effectively reduces the complexity of the routing and improves the utilization rate of the array.And,the overhead of on-chip memory is reduced by means of compressing weight coefficients and configurations.In the aspect of system scheduling,this thesis proposes a scheduler for weight coefficients and configurations to improve the efficiency of pipeline.Besides,a multi-mode data cache based on dynamically prefetching mechanism is designed,which can achieve high hit ratio with relatively less memory overhead and improve the performance of data access.Compared with the single Mesh routing structure,the dynamically adaptive routing structure based on computational load makes the computing performance and the PE utilization improved by 30.1%and 16.7%respectively.After the compression of configurations,the performance of system is improved 10.0%.With the memory capacity of 12KB,the hit ratio of data cache module based on the dynamically prefetching mechanism is more than 90%and the prefetching performance is improved by 39%?45%.Based on SMIC 40nm process,the results show that the minimum energy efficiency of JEPG encoding system is 0.102nJ/pixel,which supports 17fps-87fps.Besides,the power comsumption of H.264 encoding system is 197.63mW at 200MHz&1.0V,supporting 480P/720P/1080P at 30fps.