Research And Implementation Of High Speed Image Acquisition And Processing Technology Based On FPGA

High speed image processing system is applied in areas such as optical observation of particle movement,high-speed flight measurement of weapons,monitoring of explosion process,records of vehicles crash and so on.Through the study of high-speed image sequence,we can get the specific motion state of high-speed moving object at a certain moment,which plays a critical role in judging the key information of high-speed moving target.In the acquisition and processing data of high-speed image,multi-core CPU,multi-core GPU and multi-core DSP are usually used to achieve high-speed image processing,but due to their serial execution instructions and heavy power consumption,application of them is limited in some areas of higher requirements on volume and power.FPGA has become a new trend in high-speed data processing by parallel operation,low power consumption,and high processing speed.Especially the combination of So C and FPGA has greatly improved the efficiency of data processing.In the transmission of high-speed data,Ethernet,PCIe and Rapid IO are the major three main bus.However,both Ethernet's delay and the pin number of PICe are too high.Rapid IO has all the advantages of Ethernet and PCIe,which makes Rapid IO has become the best choice of an embedded system backplane or chip interconnection system.The design of this system,based on So C heterogeneous operation,has completed the development of high-speed video capture and processing system.It has completed high-speed video sequence capture,and high-speed video signal board-level interconnection through the rapid IO,the board-level pipeline process.It has not only saved interconnection costs,reduced system power,but also has a low latency,and low jitter.The system uses the So C on the FPGA platform to achieve heterogeneous acceleration function as well as the analysis and processing of real-time and high-speed video signal.The main work of this thesis includes the following three aspects: The first one is the completion of high-speed image acquisition and format conversion.This thesis analyzes the working mode and internal register configuration of the NOIP1SN0300 A sensor in ON semi,and by the SPI synchronous serial port and the So C,functions of the sensor are configured and initialized.The data output protocol of the image sensor is studied and analyzed,and custom logic and timing constraints of the FPGAis designed to achieve the format conversion and reception of So C FPGA for image sensor video data.The second one is the achievement of the backplane transmission of high-speed image data.The Rapid IO protocol standard,the three layers of the logical layer,transport layer and physical layer of Rapid IO are deeply analyzed.The Rapid IO standard packet exchange protocol,the transaction packs exchange,the I / O transaction operation type,and the error management mechanism are all studied in detail.Based on the FPGA platform,the custom logic design of the send and receive operation of each operation interface is completed,and the high speed video image data backplane transmission system based on Rapid IO specification is realized.Finally,the image enhancement heterogeneous acceleration is achieved based on So C FPGA platform.The Open CL isomorphic technique is implemented,and the de-hazing algorithm based on the illumination of the veil is used.The algorithm is different from the traditional method of using farthest point as the atmospheric value,and the guided filter method is used to achieve efficient and fast image de-hazing.In this thesis,the practical parallel algorithm is analyzed,and on the FPGA platform the parallel acceleration of image enhancement is realized by the main program(x86 or ARM)instruction.