Circuit Implementation Of SURF Feature Detection Based On FPGA

Image local feature extraction and description is a hot spot in the field of digital image processing.Rencently,a variety of local image feature extraction algorithms come out.However,in practical engineering applications,it is difficult to make an algorithm meet the requirements of a number of performance indicators.We usually need to optimize the algorithm and make the compromise between algorithm complexity and performance.SURF(Speeded Up Robust Features)is a widely used feature extraction algorithm with local scale invariance.The algorithm is easy to be implemented on the general-purpose processor.However,the implementation on the general-purpose processor could not meet the speed of real-time processing.Large capacity data storage and floating-point arithmetic is the bottleneck to improve the speed of the SURF algorithm.The main work of this paper is to design the hardware implementation based on Xilinx ZYNQ platform.The SURF algorithm is implemented in hardware circuit at first and is packaged into IP core using the AXI4-Stream interface.The overall hardware structure building is completed based on IP core.The paper verifies and evaluates design in the embedded environment.The hardware design is mainly focused on high-capacity data storage and floating-point operations.The paper designs an fixed-point arithmetic structure.the algorithm is optimized to make it more suitable for hardware implementation.The SURF circuit is divided into four modules: Integration image module,Data Buffer module,Hessian Determinant module and Non-maximum Suppression module.A data buffering structure is designed to storage large amount of data.The method of four-scale paralleled is adopted to improve the speed.In the final test on the board,the maximum operating frequency of the hardware can reach 40 MHz.When the clock is set to 33 MHz,the processing speed can reach more than 100 fps.The verification on the board is in the embedded environment.Test data and results data is saved in memory through DMA IP during test.