Hardware Design And Implementation Of Speech Recognition SoC

Speech recognition SoC is one of the most important research directions in the field of speech recognition technology.It has the advantages of low power consumption,small size and high reliability.It is an excellent platform for speech recognition technology.However,at present,there are few researches on Chinese speech recognition SoC in China,and most of the existing Chinese speech recognition SoC has poor real-time performance and poor recognition performance.This paper designs a SoC architecture which is suitable for speech recognition system by analyzing the Chinese speech recognition system based on GMM-HMM,and completes hardware programming,simulation,layout design and fabrication of the chip.The chip takes Andes N10 MCU as the core,and uses APB as the on-chip bus.In addition,the chip integrates a large number of peripheral devices as an extension,including ADC,I2 C,GPIO,SPI,TIMER,floating point acceleration module and so on.This paper focuses on the research of algorithm,hardware design and implementation of SoC,system simulation and chip test.The main work includes the following aspects.Firstly,through the analysis of commonly used speech recognition algorithm,this paper constructs a speech recognition system which is suitable to be achieved in SoC,and reduces system delay by optimizing the algorithm.Secondly,through the analysis of system requirements,this paper completes hardware/software partition of the system and So C design.In order to solve the problem of high delay,a specific hardware circuit is designed to accelerate the computation of the probability density.The SRAM is used as the program space to speed up the reading speed.In order to solve the problem of high power consumption,the design of asynchronous clock and gating clock is used to control the opening and closing of each module to achieve the purpose of controlling the power consumption of the system.Thirdly,this paper defines interface and timing of each module of chip,completes the hardware programming of SoC,and verifies the function of module by importing sensitive data and imitating slave module.In addtion,the resource occupation and power consumption simulation of the chip logic project are analyzed.Fourly,this paper completes layout design and fabrication of the chip,tests the performance of the chip such as power consumption,real time and recognition rate and compared with typical Chinese speech recognition chip.In this paper,Verilog hardware description language is used to realize the chip's logic engineering.Besides,the paper verifies the function of each module and analyses their power consumption.Finally,the chip is taped out in TSMC 0.18 um process.The chip's test results show that the power consumption of the chip is about 244.83 mW,its recognition rate can reach 95.5%,and can realize real-time speech recognition.