The Optimization Of Data Channel Architecture On Stream Processor For Graph Search

As the internet technology widly and deeply used,all kinds of information data is explosive growing.The spatial locality and the temporal locality is getting more inappropriate while dealing Bigdata problem,whith the traditional processor architecture used as a mainly technology.Therefore,the research on the architecture of the microprocessor system for large data problems has become a hot topic in the academic circle.Graph problem is a typical problem in bigdata problem,especially as the BFS algorithm in graph search problem becoming the core search algorithm in Graph500,it plays an important role in many bigdata applications.The stream processor architecture whith has been considered to be more effectivly to the processing of large data problems,is now getting more attention.Therefore,based on the basic architecture of the bigdata stream processor,the datapath is designed and optimized with high bandwidth and low latency.This paper has the following aspects of research:Firstly,designed a series of experimental methods to analyze the performance of the stream processor architecture.Although the basic method for analysising processor performance has been a consummate technology,however,when it comes to different processor architectures,the specific methods and details for analysing their performance are still required to be studied according to the design details.This paper mainly using the method of analyzing the average queue length of FIFO to judge the congestion in the processor data path.And also this paper judge the performance of the processor's data path by analyzing the average delay of the module.Secondly,analys and select the optimal inventory control strategy by studying the BFS parallel algorithm in the processor specific memory access mode.The different memory access mode can lead to a total different MIG bandwidth.So by this studing,we improves the overall bandwidth of the data path through the research and optimization of the access memory strategy.Processor performance has been improved by 51%.Thirdly,by studying and mining the parallelism of the functional components,the delay of the data path has been reduced.In this paper,we study the parallel of Load/Store Interface module,and discuss the importance of parallel in different BFS algorithms.Designing and implementing a connector by using the method of pipeline,we get a excellent promotion to achieve high bandwidth of data path.Lastly,in view of the demand of multi node parallel processing BFS algorithm,a set of high degree of parallelism remote access memory system has been designed.And according to the mechanism design and implement the new structure of data path of the stream processor.Processor performance is 0.89 MTEPs 5.23 MTEPs and 74.44 MTEPs.