Research On Self-test Technology Of MEMS Seismic Sensors

The decades of accumulated experience and the ever-increasing manufacturing process have contributed to the rapid updating of MEMS seismic sensor research results.At the same time,these results also have penetrated into the military,civilian products and many other applications.In contrast,the development of seismic sensor test technology is lagging behind,and the traditional test method has been unable to adapt to the rapid and accurate test needs.In this context,this subject designed a seismic sensor system which can realize self-test function.This project designed a method of the self-test aiming at seismic sensors.For the sake of the sinusoidal signal using for testing the static parameters and dynamic parameters of seismic sensors,a pure digital technique based data generator was applied to establish the self-test module.The data generator was fabricated on the same chip with the interface circuit.The sine wave was generated by a digital resonator.The multi-bit signal was converted into a signal stream by a sigma-delta modulator.The voltage affected on the sensor sensitive structure in the form of electrostatic force feedback,converted to the equivalent acceleration signal to be detected.The sigma-delta modulator is embedded in the resonator to reduce the chip area and the computation time.By adjusting the parameters of the signal generator,the magnitude and frequency of the sinusoidal signal can be accurately determined to accommodate different static and dynamic parametric tests.In order to verify the applicability of the self-test module,this paper designs a closed-loop sigma-delta digital interface circuit of seismic sensor.Non-limiting structure was adopted to reduce the difficulty of system parameter acquisition.Phase compensator was introduced to ensure stability,at the same time.Based on the analysis of the main source of distortion in the system,the transistor-level circuit design was performed on sub-modules such as charge amplifiers,followers,phase compensators,integrators,quantizers,and timing circuits.SpectreVerilog was used to simulate the circuit.The output noise density of the interface circuit within the signal bandwidth was less than 250nV/Hz^1/2.The harmonic distortion was less than-120dB.The performance can meet the needs.While the self-test module worked properly.