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Study Of Design For Testability Based IP Watermarking Techniques

Posted on:2018-10-25Degree:MasterType:Thesis
Country:ChinaCandidate:X N HuangFull Text:PDF
GTID:2348330533469361Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
Nowadays,Integrated Circuit design has entered System-on-a-Chip era and intellectual property reuse technology has been widely used.The IP reuse technology improves the design efficiency and reduces time-to-market.While the trade of IP is common today,IP is easy to be illegally used.Digital watermarking is an effective IP protect method.Digital watermarking technique can embed the IP owner's information into the circuit to protect IP from illegal use.In digital watermarking,constraint-based watermarking technique is a popular technique to embed watermark.In constraint-based watermarking,According to watermarking detection mechanism,watermarking can be divided into static watermarking and dynamic watermarking.Finite state machine(FSM)watermarking and design for testability(DFT)watermarking are the two most common dynamic watermarking techniques.Compared with FSM watermarking,the overhead due to watermark is more easily controlled in DFT watermarking.Therefore,the dissertation focuses on the DFT watermarking.A new DFT watermarking scheme is proposed.The IP owner's information is first transformed into watermark sequence.During the process of scan chain ordering for test power optimization,the watermark is embedded by constraining the connection style of two scan cells.The watermarking process is interwoven with the optimization process to minimize the test power overhead due to watermarking.The watermark can be detected in field after the integrated circuit is packaged.When 64-bits and 128-bits watermark is embedded,the probability of coincidence is 5.42E-20 and 2.94E-39,respectively.The watermarking scheme can provide strong authorship proof because the probability of coincidence is very low.Typical attack scenarios are discussed.Experimental result shows when 64-bits and 128-bits watermark is embedded respectively,the watermarking scheme incurs sufficiently low overhead on test power.In the process of conducting the above experiment,the shortcoming of the original scan cell ordering method which is the basis of the proposed watermarking scheme is exposed.When the method is applied to the benchmark which has big test data,it is time-consuming.The method is improved in terms of time complexity.By reducing the number of candidate scan cells in the process of ordering,the time complexity is improved.Based on the improved method,the corresponding improved watermarking scheme is proposed.By introducing the parameter K,The time complexity is reduced from O(N2)to O(KN).A suitable value for K where the transitions overhead is as small as possible while over a half of computation time can be reduced is found.Experiment result shows while over a half of computation time is saved,the improved watermarking scheme also incurs sufficiently low overhead on test power.
Keywords/Search Tags:IP protection, digital watermarking, DFT watermarking, scan cell ordering
PDF Full Text Request
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